Implement Plane Gamma feature for BDW and Gen9 platforms.
v2: Used newly added drm_color_lut_ext structure for enhanced
precision for Gamma LUT entries.
v3: Rebase
v4: Used extended function for LUT extraction (pointed by
Alexandru).
v5: Rebase
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 5 +++-
drivers/gpu/drm/i915/i915_reg.h | 25 ++++++++++++++++
drivers/gpu/drm/i915/intel_color.c | 57 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_display.c | 4 +++
drivers/gpu/drm/i915/intel_sprite.c | 4 +++
5 files changed, 94 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ef7410c..bf61c2e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -117,7 +117,10 @@
}
#define BDW_COLORS \
- .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
+ .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }, \
+ .plane_color = { .plane_degamma_lut_size = 0, \
+ .plane_gamma_lut_size = 16 }
+
#define CHV_COLORS \
.color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 477dfda..0beed42 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -257,6 +257,10 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
DISPLAY_MMIO_BASE(dev_priv))
+/* Plane Gamma Registers */
+#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
+#define _MMIO_PLANE_GAMC16(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4)
+
#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
#define _MASKED_FIELD(mask, value) ({ \
if (__builtin_constant_p(mask)) \
@@ -10156,6 +10160,27 @@ enum skl_power_gate {
#define PRE_CSC_GAMC_INDEX(pipe) _MMIO_PIPE(pipe, _PRE_CSC_GAMC_INDEX_A,
_PRE_CSC_GAMC_INDEX_B)
#define PRE_CSC_GAMC_DATA(pipe) _MMIO_PIPE(pipe,
_PRE_CSC_GAMC_DATA_A, _PRE_CSC_GAMC_DATA_B)
+/* Plane Gamma in Gen9+ */
+#define _PLANE_GAMC_1_A 0x701d0
+#define _PLANE_GAMC_1_B 0x711d0
+#define _PLANE_GAMC_2_A 0x702d0
+#define _PLANE_GAMC_2_B 0x712d0
+#define _PLANE_GAMC_1(pipe) _PIPE(pipe, _PLANE_GAMC_1_A, _PLANE_GAMC_1_B)
+#define _PLANE_GAMC_2(pipe) _PIPE(pipe, _PLANE_GAMC_2_A, _PLANE_GAMC_2_B)
+#define PLANE_GAMC(pipe, plane, i) \
+ _MMIO_PLANE_GAMC(plane, i, _PLANE_GAMC_1(pipe), _PLANE_GAMC_2(pipe))
+
+#define _PLANE_GAMC16_1_A 0x70210
+#define _PLANE_GAMC16_1_B 0x71210
+#define _PLANE_GAMC16_2_A 0x70310
+#define _PLANE_GAMC16_2_B 0x71310
+#define _PLANE_GAMC16_1(pipe) _PIPE(pipe, _PLANE_GAMC16_1_A, \
+ _PLANE_GAMC16_1_B)
+#define _PLANE_GAMC16_2(pipe) _PIPE(pipe, _PLANE_GAMC16_2_A, \
+ _PLANE_GAMC16_2_B)
+#define PLANE_GAMC16(pipe, plane, i) _MMIO_PLANE_GAMC16(plane, i, \
+ _PLANE_GAMC16_1(pipe), _PLANE_GAMC16_2(pipe))
+
/* pipe CSC & degamma/gamma LUTs on CHV */
#define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
#define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 0f8cb18..c756cd9 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -562,6 +562,59 @@ static void broadwell_load_luts(const struct
intel_crtc_state *crtc_state)
}
}
+static void bdw_load_plane_gamma_lut(const struct drm_plane_state *state,
+ u32 offset)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ u32 i, lut_size =
+ INTEL_INFO(dev_priv)->plane_color.plane_gamma_lut_size;
+
+ if (state->gamma_lut) {
+ struct drm_color_lut_ext *lut =
+ (struct drm_color_lut_ext *)state->gamma_lut->data;
+
+ for (i = 0; i < lut_size; i++) {
+ u32 word =
+ drm_color_lut_extract_ext(lut[i].red, 10) << 20 |
+ drm_color_lut_extract_ext(lut[i].green, 10) << 10 |
+ drm_color_lut_extract_ext(lut[i].blue, 10);
+
+ I915_WRITE(PLANE_GAMC(pipe, plane, i), word);
+ }
+
+ /* Program the max register to clamp values > 1.0. */
+ i = lut_size - 1;
+ I915_WRITE(PLANE_GAMC16(pipe, plane, 0),
+ drm_color_lut_extract_ext(lut[i].red, 16));
+ I915_WRITE(PLANE_GAMC16(pipe, plane, 1),
+ drm_color_lut_extract_ext(lut[i].green, 16));
+ I915_WRITE(PLANE_GAMC16(pipe, plane, 2),
+ drm_color_lut_extract_ext(lut[i].blue, 16));
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 10) - 1)) / (lut_size - 1);
+
+ I915_WRITE(PLANE_GAMC(pipe, plane, i),
+ (v << 20) | (v << 10) | v);
+ }
+
+ I915_WRITE(PLANE_GAMC16(pipe, plane, 0), (1 << 16) - 1);
+ I915_WRITE(PLANE_GAMC16(pipe, plane, 1), (1 << 16) - 1);
+ I915_WRITE(PLANE_GAMC16(pipe, plane, 2), (1 << 16) - 1);
+ }
+}
+
+/* Loads the palette/gamma unit for the CRTC on Broadwell+. */
+static void broadwell_load_plane_luts(const struct drm_plane_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+
+ bdw_load_plane_gamma_lut(state,
+
INTEL_INFO(dev_priv)->plane_color.plane_degamma_lut_size);
+}
+
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
@@ -873,6 +926,10 @@ void intel_plane_color_init(struct drm_plane *plane)
{
struct drm_i915_private *dev_priv = to_i915(plane->dev);
+ if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) ||
+ IS_BROXTON(dev_priv))
+ dev_priv->display.load_plane_luts = broadwell_load_plane_luts;
+
drm_plane_color_create_prop(plane->dev, plane);
/* Enable color management support when we have degamma or gamma LUTs.
*/
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 61acbaf..e922644 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14395,6 +14395,10 @@ static bool i9xx_plane_has_fbc(struct drm_i915_private
*dev_priv,
DRM_MODE_ROTATE_0,
supported_rotations);
+ /* Add Plane Color properties */
+ if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
+ intel_plane_color_init(&plane->base);
+
drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
return plane;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index 268fb34..121da10 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -2319,6 +2319,10 @@ struct intel_plane *
BIT(DRM_MODE_BLEND_PREMULTI) |
BIT(DRM_MODE_BLEND_COVERAGE));
+ /* Add Plane Color properties */
+ if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
+ intel_plane_color_init(&plane->base);
+
drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
return plane;
--
1.9.1
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