Quoting Daniele Ceraolo Spurio (2019-03-21 22:14:20)
>
>
> On 3/21/19 3:11 PM, Chris Wilson wrote:
> > Quoting Daniele Ceraolo Spurio (2019-03-21 22:02:06)
> >> The upcoming unified GuC FW will require us to send video engine enable
> >> masks to GuC for its initialization.
> >>
> >> For consistency, just set the runtime_info enable masks for all gens.
> >> We'll then be able to directly use those in the GuC setup
> >>
> >> Cc: Michal Wajdeczko <michal.wajdec...@intel.com>
> >> Cc: John Spotswood <john.a.spotsw...@intel.com>
> >> Cc: Eric Betancourt <eric.s.betanco...@intel.com>
> >> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/intel_device_info.c | 8 +++++++-
> >> 1 file changed, 7 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> >> b/drivers/gpu/drm/i915/intel_device_info.c
> >> index eddf83807957..836184d6538e 100644
> >> --- a/drivers/gpu/drm/i915/intel_device_info.c
> >> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> >> @@ -872,8 +872,14 @@ void intel_device_info_init_mmio(struct
> >> drm_i915_private *dev_priv)
> >> unsigned int i;
> >> u32 media_fuse;
> >>
> >> - if (INTEL_GEN(dev_priv) < 11)
> >> + if (INTEL_GEN(dev_priv) < 11) {
> >> + RUNTIME_INFO(dev_priv)->vdbox_enable =
> >> + (info->engine_mask & GENMASK(VCS0 + I915_MAX_VCS,
> >> VCS0)) >> VCS0;
>
> D'oh!
>
> Thanks for catching this, GuC just ignores the higher bits and didn't
> complain, so I missed it.
Having demonstrated it's a simple mapping, do we need to store it
separately?
#define VDBOX_MASK(info) \
(((info)->engine_mask & \
GENMASK(VCS0 + I915_MAX_VCS - 1, VCS0)) >> VCS0)
etc
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
