>
> + /*
> + * On Geminilake once the CDCLK gets as low as 79200
> + * picture gets unstable, despite that values are
> + * correct for DSI PLL and DE PLL.
> + */
> + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
> + IS_GEMINILAKE(dev_priv))
> + min_cdclk = max(158400, min_cdclk);
> +
> if (min_cdclk > dev_priv->max_cdclk_freq) {
> DRM_DEBUG_KMS("required cdclk (%d kHz) exceeds max (%d kHz)\n",
> min_cdclk, dev_priv->max_cdclk_freq);
>Hey,
>With a bit of love to the commit's first line, I think this patch looks good.
>:)
Yes, I've just sent a v2 version with a bit more detailed explanation :)
>Is this behavior documented somewhere?
In fact no, there are similar issues with VLV so I actually simply
used similar approach. We were first suspecting that we get to high
DSI PLL dividers due to agressive rounding, so tried different ratios,
however no success. Also CDCLK clocking seems to be correct, however
display looks like complete garbage. Any other CDCLK clock > 79200 for DSI
solves the issue.
-Stanislav
>~Maarten
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