Quoting Ville Syrjala (2019-04-15 15:16:41) > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > Since SKL the eLLC has been sitting on the far side of the system > agent, meaning the display engine can utilize it. Let's enable that. > > I chose WB for the caching mode, because my numbers are indicating > that WT might actually be WB and WC might actually be UC. I'm not > 100% sure that is indeed the case but at least my simple rendercopy > based benchmark didn't see any difference in performance. > > Also if I configure things to do LLCeLLC+WT I still get cache dirt > on my screen, suggesting that is in fact operating in WB mode > anyway. This is also the reason I had to fix the MOCS target cache > to really say PTE rather than LLC+eLLC. > > Caveat: I've not benchmarked any real workloads. IIRC Eero did > benchmark an earlier version, but that didn't have the PTE vs. > LLC+eLLC MOCS fix so it wasn't actually doing the right thing > most likely. > > Cc: Eero Tamminen <eero.t.tammi...@intel.com> > Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com> Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk> -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
