On Wed, May 29, 2019 at 03:20:56PM +0530, Swati Sharma wrote:
> In this patch, hw gamma blob is created for i965.
>
> v4: -No need to initialize *blob [Jani]
> -Removed right shifts [Jani]
> -Dropped dev local var [Jani]
> v5: -Returned blob instead of assigning it internally
> within the function [Ville]
> -Renamed i965_get_color_config() to i965_read_lut() [Ville]
> -Renamed i965_get_gamma_config_10p6() to i965_read_gamma_lut_10p6()
> [Ville]
>
> Signed-off-by: Swati Sharma <swati2.sha...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_color.c | 39
> ++++++++++++++++++++++++++++++++++++++
> 2 files changed, 42 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b58c66d..7988fa5 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3584,6 +3584,9 @@ enum i915_power_well_id {
> #define _PALETTE_A 0xa000
> #define _PALETTE_B 0xa800
> #define _CHV_PALETTE_C 0xc000
> +#define PALETTE_RED_MASK REG_GENMASK(23, 16)
> +#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
> +#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
> #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> _PICK((pipe), _PALETTE_A, \
> _PALETTE_B, _CHV_PALETTE_C) + \
> diff --git a/drivers/gpu/drm/i915/intel_color.c
> b/drivers/gpu/drm/i915/intel_color.c
> index 6ed851b..3ec84af 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -1505,6 +1505,44 @@ static void chv_read_luts(struct intel_crtc_state
> *crtc_state)
> crtc_state->base.gamma_lut = chv_read_cgm_gamma_lut(crtc_state);
> }
>
> +static struct drm_property_blob *
> +i965_read_gamma_lut_10p6(struct intel_crtc_state *crtc_state)
i965_read_lut_10p6() would match the name of the counterpart better.
I think crtc_state can be const in all of these functions. Or you could
pass just the crtc itself rather than its state.
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + u32 i, val1, val2, lut_size =
> INTEL_INFO(dev_priv)->color.gamma_lut_size;
> + enum pipe pipe = crtc->pipe;
> + struct drm_property_blob *blob;
> + struct drm_color_lut *blob_data;
> +
> + blob = drm_property_create_blob(&dev_priv->drm,
> + sizeof(struct drm_color_lut) * lut_size,
> + NULL);
> + if (IS_ERR(blob))
> + return NULL;
> +
> + blob_data = blob->data;
> +
> + for (i = 0; i < lut_size - 1; i++) {
> + val1 = I915_READ(PALETTE(pipe, 2 * i + 0));
> + val2 = I915_READ(PALETTE(pipe, 2 * i + 1));
> +
> + blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val1) << 8 |
> REG_FIELD_GET(PALETTE_RED_MASK, val2);
> + blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val1) <<
> 8 | REG_FIELD_GET(PALETTE_GREEN_MASK, val2);
> + blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val1) << 8
> | REG_FIELD_GET(PALETTE_BLUE_MASK, val2) ;
> + }
> +
> + return blob;
> +}
> +
> +static void i965_read_luts(struct intel_crtc_state *crtc_state)
> +{
> + if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> + crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + else
> + crtc_state->base.gamma_lut =
> i965_read_gamma_lut_10p6(crtc_state);
> +}
> +
> void intel_color_init(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -1522,6 +1560,7 @@ void intel_color_init(struct intel_crtc *crtc)
> dev_priv->display.color_check = i9xx_color_check;
> dev_priv->display.color_commit = i9xx_color_commit;
> dev_priv->display.load_luts = i965_load_luts;
> + dev_priv->display.read_luts = i965_read_luts;
> } else {
> dev_priv->display.color_check = i9xx_color_check;
> dev_priv->display.color_commit = i9xx_color_commit;
> --
> 1.9.1
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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