We need to properly track PCH PLL sharing configs, and generally set up
PCH PLL state at init time as part of the state readout process.
I-told-you-so-by: Daniel Vetter <daniel.vet...@ffwll.ch>
Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
---
drivers/gpu/drm/i915/intel_display.c | 51 ++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 8b55427..208dde4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6915,6 +6915,54 @@ static int ironlake_crtc_clock_get(struct drm_crtc *crtc)
return clock;
}
+static bool ironlake_crtc_pll_get(struct drm_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ u32 dpll_sel;
+
+ if (HAS_PCH_IBX(dev_priv->dev))
+ intel_crtc->pch_pll = &dev_priv->pch_plls[intel_crtc->pipe];
+
+ if (HAS_PCH_CPT(dev_priv->dev)) {
+ dpll_sel = I915_READ(PCH_DPLL_SEL);
+
+ switch (intel_crtc->pipe) {
+ case PIPE_A:
+ if ((dpll_sel & TRANSA_DPLL_ENABLE) &&
+ (dpll_sel & TRANSA_DPLLB_SEL))
+ intel_crtc->pch_pll = &dev_priv->pch_plls[1];
+ else if (dpll_sel & TRANSA_DPLL_ENABLE)
+ intel_crtc->pch_pll = &dev_priv->pch_plls[0];
+ break;
+ case PIPE_B:
+ if ((dpll_sel & TRANSB_DPLL_ENABLE) &&
+ (dpll_sel & TRANSB_DPLLB_SEL))
+ intel_crtc->pch_pll = &dev_priv->pch_plls[1];
+ else if (dpll_sel & TRANSB_DPLL_ENABLE)
+ intel_crtc->pch_pll = &dev_priv->pch_plls[0];
+ break;
+ case PIPE_C:
+ if ((dpll_sel & TRANSC_DPLL_ENABLE) &&
+ (dpll_sel & TRANSC_DPLLB_SEL))
+ intel_crtc->pch_pll = &dev_priv->pch_plls[1];
+ else if (dpll_sel & TRANSC_DPLL_ENABLE)
+ intel_crtc->pch_pll = &dev_priv->pch_plls[0];
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (intel_crtc->pch_pll) {
+ intel_crtc->pch_pll->refcount++;
+ intel_crtc->pch_pll->active = 1;
+ return true;
+ }
+
+ return false;
+}
+
static bool ironlake_crtc_get_mode(struct drm_crtc *crtc,
struct drm_display_mode *mode)
{
@@ -6943,6 +6991,9 @@ static bool ironlake_crtc_get_mode(struct drm_crtc *crtc,
mode->clock = ironlake_crtc_clock_get(crtc);
+ if (!ironlake_crtc_pll_get(crtc))
+ return false;
+
drm_mode_set_name(mode);
return true;
--
1.7.9.5
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