On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> According to the spec when initializing the display in TGL we should
> not
> set PORT_CL_DW12 for the Aux channel of the combo PHYs. We will re-
> use the
> power well hooks from ICL so just check for IS_TIGERLAKE() inside it.
BSpec: 4301
It took me a while to find it :P
>
> Cc: Imre Deak <imre.d...@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_power.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index be3d4d1eece2..f040a74349df 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -458,8 +458,10 @@ icl_combo_phy_aux_power_well_enable(struct
> drm_i915_private *dev_priv,
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx));
>
> - val = I915_READ(ICL_PORT_CL_DW12(port));
> - I915_WRITE(ICL_PORT_CL_DW12(port), val | ICL_LANE_ENABLE_AUX);
> + if (!IS_TIGERLAKE(dev_priv)) {
You probably want to change this to if (INTEL_GEN(dev_priv) < 12) or
something like to carry this change to future platforms.
With that:
Reviewed-by: José Roberto de Souza <jose.so...@intel.com>
> + val = I915_READ(ICL_PORT_CL_DW12(port));
> + I915_WRITE(ICL_PORT_CL_DW12(port), val |
> ICL_LANE_ENABLE_AUX);
> + }
>
> hsw_wait_for_power_well_enable(dev_priv, power_well);
>
> @@ -486,8 +488,10 @@ icl_combo_phy_aux_power_well_disable(struct
> drm_i915_private *dev_priv,
> enum port port = ICL_AUX_PW_TO_PORT(pw_idx);
> u32 val;
>
> - val = I915_READ(ICL_PORT_CL_DW12(port));
> - I915_WRITE(ICL_PORT_CL_DW12(port), val & ~ICL_LANE_ENABLE_AUX);
> + if (!IS_TIGERLAKE(dev_priv)) {
> + val = I915_READ(ICL_PORT_CL_DW12(port));
> + I915_WRITE(ICL_PORT_CL_DW12(port), val &
> ~ICL_LANE_ENABLE_AUX);
> + }
>
> val = I915_READ(regs->driver);
> I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
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