On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> From: Mahesh Kumar <mahesh1.ku...@intel.com>
>
> Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy
> ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14
> are
> mapped to TC ports.
Reviewed-by: José Roberto de Souza <jose.so...@intel.com>
>
> Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
> Signed-off-by: Mahesh Kumar <mahesh1.ku...@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.h | 2 ++
> drivers/gpu/drm/i915/display/intel_gmbus.c | 20
> ++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 4 +++-
> 3 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 270b1f18dedd..231d8595845a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -45,6 +45,8 @@ enum i915_gpio {
> GPIOK,
> GPIOL,
> GPIOM,
> + GPION,
> + GPIOO,
> };
>
> /*
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c
> b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 4f6a9bd5af47..b42c79aea61a 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -94,11 +94,25 @@ static const struct gmbus_pin gmbus_pins_mcc[] =
> {
> [GMBUS_PIN_9_TC1_ICP] = { "dpc", GPIOJ },
> };
>
> +static const struct gmbus_pin gmbus_pins_tgp[] = {
> + [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
> + [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
> + [GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
> + [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
> + [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
> + [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
> + [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> + [GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
> + [GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
> +};
> +
> /* pin is expected to be valid */
> static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private
> *dev_priv,
> unsigned int pin)
> {
> - if (HAS_PCH_MCC(dev_priv))
> + if (HAS_PCH_TGP(dev_priv))
> + return &gmbus_pins_tgp[pin];
> + else if (HAS_PCH_MCC(dev_priv))
> return &gmbus_pins_mcc[pin];
> else if (HAS_PCH_ICP(dev_priv))
> return &gmbus_pins_icp[pin];
> @@ -119,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct
> drm_i915_private *dev_priv,
> {
> unsigned int size;
>
> - if (HAS_PCH_MCC(dev_priv))
> + if (HAS_PCH_TGP(dev_priv))
> + size = ARRAY_SIZE(gmbus_pins_tgp);
> + else if (HAS_PCH_MCC(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_mcc);
> else if (HAS_PCH_ICP(dev_priv))
> size = ARRAY_SIZE(gmbus_pins_icp);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 4588df9e11de..c554df69f289 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3254,8 +3254,10 @@ enum i915_power_well_id {
> #define GMBUS_PIN_10_TC2_ICP 10
> #define GMBUS_PIN_11_TC3_ICP 11
> #define GMBUS_PIN_12_TC4_ICP 12
> +#define GMBUS_PIN_13_TC5_TGP 13
> +#define GMBUS_PIN_14_TC6_TGP 14
>
> -#define GMBUS_NUM_PINS 13 /* including 0 */
> +#define GMBUS_NUM_PINS 15 /* including 0 */
> #define GMBUS1 _MMIO(dev_priv->gpio_mmio_base
> + 0x5104) /* command/status */
> #define GMBUS_SW_CLR_INT (1 << 31)
> #define GMBUS_SW_RDY (1 << 30)
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