Quoting Kumar Valsan, Prathap (2019-08-01 21:33:44) > On Tue, Jul 30, 2019 at 12:21:51PM +0100, Chris Wilson wrote: > > Recently discovered in commit bdae33b8b82b ("drm/i915: Use maximum write > > flush for pwrite_gtt") was that we needed to our full write barrier > > before changing the GGTT PTE to ensure that our indirect writes through > > the GTT landed before the PTE changed (and the writes end up in a > > different page). That also applies to our GGTT relocation path. > > Chris, > > As i understand, changing the GGTT PTE also an indirect write. If so, isn't a > wmb() > should be good enough.
Ha! If only that was true. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx