On Fri, Aug 23, 2019 at 01:20:36AM -0700, Lucas De Marchi wrote: > From: José Roberto de Souza <jose.so...@intel.com> > > From BDW+ the PSR registers moved from DDIA to transcoder, so any port > with a eDP panel connected can have PSR, so lets remove this > limitation. > > Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> > Cc: Rodrigo Vivi <rodrigo.v...@intel.com> > Signed-off-by: José Roberto de Souza <jose.so...@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com> > Reviewed-by: Anshuman Gupta <anshuman.gu...@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 81e3619cd905..0172b82858d9 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -588,11 +588,9 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, > > /* > * HSW spec explicitly says PSR is tied to port A. > - * BDW+ platforms have a instance of PSR registers per transcoder but > - * for now it only supports one instance of PSR, so lets keep it > - * hardcoded to PORT_A > + * BDW+ platforms have a instance of PSR registers per transcoder. > */ > - if (dig_port->base.port != PORT_A) { > + if (IS_HASWELL(dev_priv) && dig_port->base.port != PORT_A) {
Based on an earlier discussion with Art, before TGL PSR is not supposed to be used anywhere else than port A. Art could you confirm that? > DRM_DEBUG_KMS("PSR condition failed: Port not supported\n"); > return; > } > -- > 2.23.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx