For icl+, add hw read out to create hw blob of gamma
lut values. icl+ platforms supports multi segmented gamma
mode, add hw lut creation for this mode.
This will be used to validate gamma programming using dsb
(display state buffer) which is a tgl feature.
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning it internally within the
function [Ville]
-Renamed icl_get_color_config() to icl_read_luts() [Ville]
-Renamed bdw_get_gamma_config() to bdw_read_lut_10() [Ville]
v9: -Added hw lut creation for multi-seg gamma mode
Signed-off-by: Swati Sharma <swati2.sha...@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 88 +++++++++++++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
2 files changed, 86 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 621f540..8d6f3c4 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -837,7 +837,6 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut
*color)
u32 i;
/*
- *
* Program Fine segment (let's call it seg2)...
*
* Fine segment's step is 1/(128 * 256) ie 1/(128 * 256), 2/(128*256)
@@ -890,12 +889,10 @@ static void icl_load_luts(const struct intel_crtc_state
*crtc_state)
case GAMMA_MODE_MODE_8BIT:
i9xx_load_luts(crtc_state);
break;
-
case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
icl_program_gamma_superfine_segment(crtc_state);
icl_program_gamma_multi_segment(crtc_state);
break;
-
default:
bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
ivb_load_lut_ext_max(crtc);
@@ -1798,6 +1795,80 @@ static void glk_read_luts(struct intel_crtc_state
*crtc_state)
crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state,
PAL_PREC_INDEX_VALUE(0));
}
+static struct drm_property_blob *
+icl_read_lut_super_multi_seg(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ int hw_lut_size = 521;
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *blob_data;
+ u32 i, val1, val2;
+
+ I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) *
hw_lut_size,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ blob_data = blob->data;
+
+ for (i = 0; i < 9; i++) {
+ val1 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
+ val2 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
+
+ blob_data[i].red =
REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1) << 10 |
+
REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2);
+ blob_data[i].green =
REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1) << 10 |
+
REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2);
+ blob_data[i].blue =
REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1) << 10 |
+
REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2);
+ }
+
+ I915_WRITE(PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
+
+ for (i = 1; i < 257; i++) {
+ val1 = I915_READ(PREC_PAL_DATA(pipe));
+ val2 = I915_READ(PREC_PAL_DATA(pipe));
+
+ blob_data[i + 8].red =
REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1) << 10 |
+
REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2);
+ blob_data[i + 8].green =
REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1) << 10 |
+
REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2);
+ blob_data[i + 8].blue =
REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1) << 10 |
+
REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2);
+ }
+
+ for (i = 0; i < 256; i++) {
+ val1 = I915_READ(PREC_PAL_DATA(pipe));
+ val2 = I915_READ(PREC_PAL_DATA(pipe));
+
+ blob_data[i + 265].red =
REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1) << 10 |
+
REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2);
+ blob_data[i + 265].green =
REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1) << 10 |
+
REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2);
+ blob_data[i + 265].blue =
REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1) << 10 |
+
REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2);
+ }
+
+ return blob;
+}
+
+static void icl_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
+ GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
+ GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED)
+ crtc_state->base.gamma_lut =
icl_read_lut_super_multi_seg(crtc_state);
+ else
+ crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state,
PAL_PREC_INDEX_VALUE(0));
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1839,16 +1910,17 @@ void intel_color_init(struct intel_crtc *crtc)
else
dev_priv->display.color_commit = ilk_color_commit;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
- else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
+ dev_priv->display.read_luts = icl_read_luts;
+ } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
dev_priv->display.load_luts = glk_load_luts;
dev_priv->display.read_luts = glk_read_luts;
- } else if (INTEL_GEN(dev_priv) >= 8)
+ } else if (INTEL_GEN(dev_priv) >= 8) {
dev_priv->display.load_luts = bdw_load_luts;
- else if (INTEL_GEN(dev_priv) >= 7)
+ } else if (INTEL_GEN(dev_priv) >= 7) {
dev_priv->display.load_luts = ivb_load_luts;
- else {
+ } else {
dev_priv->display.load_luts = ilk_load_luts;
dev_priv->display.read_luts = ilk_read_luts;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6b8bbfd..553b71d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10297,6 +10297,12 @@ enum skl_power_gate {
#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
+#define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24)
+#define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20)
+#define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14)
+#define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10)
+#define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4)
+#define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0)
#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
_PAL_PREC_MULTI_SEG_INDEX_A, \
--
1.9.1
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