On Fri, Sep 06, 2019 at 05:21:39PM -0700, Matt Roper wrote:
> The CNL variant of this function is identical to the BXT variant aside
> from not needing to handle SSA precharge.
>
> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 46 +---------------------
> 1 file changed, 2 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 6b5b1328a3fa..f8c2a706990b 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1645,7 +1645,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private
> *dev_priv)
> * Disable SSA Precharge when CD clock frequency < 500 MHz,
> * enable otherwise.
> */
> - if (dev_priv->cdclk.hw.cdclk >= 500000)
> + if (IS_GEN9_LP(dev_priv) && dev_priv->cdclk.hw.cdclk >= 500000)
> expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
>
> if (cdctl == expected)
> @@ -1697,48 +1697,6 @@ static void bxt_uninit_cdclk(struct drm_i915_private
> *dev_priv)
> bxt_set_cdclk(dev_priv, &cdclk_state, INVALID_PIPE);
> }
>
> -static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
> -{
> - u32 cdctl, expected;
> -
> - intel_update_cdclk(dev_priv);
> - intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> -
> - if (dev_priv->cdclk.hw.vco == 0 ||
> - dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
> - goto sanitize;
> -
> - /* DPLL okay; verify the cdclock
> - *
> - * Some BIOS versions leave an incorrect decimal frequency value and
> - * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
> - * so sanitize this register.
> - */
> - cdctl = I915_READ(CDCLK_CTL);
> - /*
> - * Let's ignore the pipe field, since BIOS could have configured the
> - * dividers both synching to an active pipe, or asynchronously
> - * (PIPE_NONE).
> - */
> - cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
> -
> - expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
> - skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
> -
> - if (cdctl == expected)
> - /* All well; nothing to sanitize */
> - return;
> -
> -sanitize:
> - DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
> -
> - /* force cdclk programming */
> - dev_priv->cdclk.hw.cdclk = 0;
> -
> - /* force full PLL disable + enable */
> - dev_priv->cdclk.hw.vco = -1;
> -}
> -
> static void icl_init_cdclk(struct drm_i915_private *dev_priv)
> {
> struct intel_cdclk_state sanitized_state;
> @@ -1800,7 +1758,7 @@ static void cnl_init_cdclk(struct drm_i915_private
> *dev_priv)
> {
> struct intel_cdclk_state cdclk_state;
>
> - cnl_sanitize_cdclk(dev_priv);
> + bxt_sanitize_cdclk(dev_priv);
>
> if (dev_priv->cdclk.hw.cdclk != 0 &&
> dev_priv->cdclk.hw.vco != 0)
> --
> 2.20.1
--
Ville Syrjälä
Intel
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