Gen-12 has a new compression format, add a new modifier to indicate that.
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Matt Roper <matthew.d.ro...@intel.com>
Cc: Nanley G Chery <nanley.g.ch...@intel.com>
Cc: Jason Ekstrand <ja...@jlekstrand.net>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
---
include/uapi/drm/drm_fourcc.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 3feeaa3f987a..1f0fbf0398f6 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,17 @@ extern "C" {
#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
/*
* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
*
--
2.17.1
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