On Mon, Sep 30, 2019 at 05:19:09PM +0300, Ville Syrjälä wrote:
> On Sun, Sep 22, 2019 at 10:08:03AM -0700, Manasi Navare wrote:
> > In case of tiled displays where different tiles are displayed across
> > different ports, we need to synchronize the transcoders involved.
> > This patch implements the transcoder port sync feature for
> > synchronizing one master transcoder with one or more slave
> > transcoders. This is only enbaled in slave transcoder
> > and the master transcoder is unaware that it is operating
> > in this mode.
> > This has been tested with tiled display connected to ICL.
> >
> > v5:
> > * Add TRANSCODER_D case and MISSING_CASE (Maarten)
> > v4:
> > Rebase
> > v3:
> > * Check of DP_MST moved to atomic_check (Maarten)
> > v2:
> > * Do not use RMW, just write to the register in commit (Jani N)
> >
> > Cc: Daniel Vetter <daniel.vet...@intel.com>
> > Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> > Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
> > Cc: Matt Roper <matthew.d.ro...@intel.com>
> > Cc: Jani Nikula <jani.nik...@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> > Reviewed-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 46 ++++++++++++++++++++
> > 1 file changed, 46 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 4ff375d5852d..1ae5eafe2892 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -4426,6 +4426,49 @@ static void icl_set_pipe_chicken(struct intel_crtc
> > *crtc)
> > I915_WRITE(PIPE_CHICKEN(pipe), tmp);
> > }
> >
> > +static void icl_enable_trans_port_sync(const struct intel_crtc_state
> > *crtc_state)
> > +{
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > + u32 trans_ddi_func_ctl2_val;
> > + u8 master_select;
> > +
> > + /*
> > + * Configure the master select and enable Transcoder Port Sync for
> > + * Slave CRTCs transcoder.
> > + */
> > + if (crtc_state->master_transcoder == INVALID_TRANSCODER)
> > + return;
> > +
> > + switch (crtc_state->master_transcoder) {
> > + case TRANSCODER_A:
> > + master_select = 1;
> > + break;
> > + case TRANSCODER_B:
> > + master_select = 2;
> > + break;
> > + case TRANSCODER_C:
> > + master_select = 3;
> > + break;
> > + case TRANSCODER_D:
> > + master_select = 4;
> > + break;
>
> That's all just master_transcoder+1.
>
So just get rid of the switch statement and add master_transcoder +1?
> > + case TRANSCODER_EDP:
>
> EDP transcoder can be master. The MISSING_CASE is wrong for EDP.
Yes, EDP trans cannot be a slave but can be a master, so I guess for that case
just
have if (TRANSCODER_EDP), master_Select == 0?
Manasi
>
> > + default:
> > + MISSING_CASE(crtc_state->master_transcoder);
> > + master_select = 0;
> > + }
> > + /* Set the master select bits for Tranascoder Port Sync */
> > + trans_ddi_func_ctl2_val = (PORT_SYNC_MODE_MASTER_SELECT(master_select) &
> > + PORT_SYNC_MODE_MASTER_SELECT_MASK) <<
> > + PORT_SYNC_MODE_MASTER_SELECT_SHIFT;
> > + /* Enable Transcoder Port Sync */
> > + trans_ddi_func_ctl2_val |= PORT_SYNC_MODE_ENABLE;
> > +
> > + I915_WRITE(TRANS_DDI_FUNC_CTL2(crtc_state->cpu_transcoder),
> > + trans_ddi_func_ctl2_val);
> > +}
> > +
> > static void intel_update_pipe_config(const struct intel_crtc_state
> > *old_crtc_state,
> > const struct intel_crtc_state
> > *new_crtc_state)
> > {
> > @@ -6494,6 +6537,9 @@ static void haswell_crtc_enable(struct
> > intel_crtc_state *pipe_config,
> > if (!transcoder_is_dsi(cpu_transcoder))
> > intel_set_pipe_timings(pipe_config);
> >
> > + if (INTEL_GEN(dev_priv) >= 11)
> > + icl_enable_trans_port_sync(pipe_config);
> > +
> > intel_set_pipe_src_size(pipe_config);
> >
> > if (cpu_transcoder != TRANSCODER_EDP &&
> > --
> > 2.19.1
>
> --
> Ville Syrjälä
> Intel
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