If all pipes are fused off it means that display is disabled, similar
like we handle for GEN 7 and 8 right above.
On GEN 9 the bit 31 is "Internal Graphics Disable" and on newer GENs
it has another function, probably on GEN 9 when bit 31 is set all
the 3 pipes disable bit are set, so we can unify the handling.
Cc: Lucas De Marchi <lucas.demar...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
---
drivers/gpu/drm/i915/intel_device_info.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 85e480bdc673..c01fccfe3cca 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -972,15 +972,14 @@ void intel_device_info_runtime_init(struct
drm_i915_private *dev_priv)
enabled_mask &= ~BIT(PIPE_D);
/*
- * At least one pipe should be enabled and if there are
- * disabled pipes, they should be the last ones, with no holes
- * in the mask.
+ * If there are disabled pipes, they should be the last ones,
+ * with no holes in the mask.
*/
- if (enabled_mask == 0 || !is_power_of_2(enabled_mask + 1))
+ if (enabled_mask && !is_power_of_2(enabled_mask + 1))
DRM_ERROR("invalid pipe fuse configuration:
enabled_mask=0x%x\n",
enabled_mask);
- else
- info->pipe_mask = enabled_mask;
+
+ info->pipe_mask = enabled_mask;
}
/* Initialize slice/subslice/EU info */
--
2.23.0
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