Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@intel.com>
Cc: James Ausmus <james.aus...@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 73 +++++++++++++++++++++++++++++++--
1 file changed, 70 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 67d171456f59..662a36ff2f43 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3750,7 +3750,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+bool skl_can_enable_sagv(struct intel_atomic_state *state)
{
struct drm_device *dev = state->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -3801,8 +3801,8 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
if (skl_needs_memory_bw_wa(dev_priv) &&
plane->base.state->fb->modifier ==
- I915_FORMAT_MOD_X_TILED)
- latency += 15;
+ I915_FORMAT_MOD_X_TILED)
+ latency += 15;
/*
* If any of the planes on this pipe don't enable wm levels that
@@ -3816,6 +3816,73 @@ bool intel_can_enable_sagv(struct intel_atomic_state
*state)
return true;
}
+bool icl_can_enable_sagv(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *new_crtc_state;
+ int level, latency;
+ int i;
+ int plane_id;
+
+ if (!intel_has_sagv(dev_priv))
+ return false;
+
+ /*
+ * If there are no active CRTCs, no additional checks need be performed
+ */
+ if (hweight8(state->active_pipes) == 0)
+ return true;
+
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+
+ if (crtc->base.state->adjusted_mode.flags &
DRM_MODE_FLAG_INTERLACE)
+ return false;
+
+ if (!new_crtc_state->base.enable)
+ continue;
+
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ struct skl_plane_wm *wm =
+
&new_crtc_state->wm.skl.optimal.planes[plane_id];
+
+ /* Skip this plane if it's not enabled */
+ if (!wm->wm[0].plane_en)
+ continue;
+
+ /* Find the highest enabled wm level for this plane */
+ for (level = ilk_wm_max_level(dev_priv);
+ !wm->wm[level].plane_en; --level)
+ { }
+
+ latency = dev_priv->wm.skl_latency[level];
+
+ /*
+ * If any of the planes on this pipe don't enable wm
levels that
+ * incur memory latencies higher than
sagv_block_time_us we
+ * can't enable SAGV.
+ */
+ if (latency < dev_priv->sagv_block_time_us)
+ return false;
+ }
+ }
+
+ return true;
+}
+
+bool intel_can_enable_sagv(struct intel_atomic_state *state)
+{
+ struct drm_device *dev = state->base.dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+
+ if (INTEL_GEN(dev_priv) >= 11)
+ return icl_can_enable_sagv(state);
+
+ return skl_can_enable_sagv(state);
+}
+
static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
const u64 total_data_rate,
--
2.17.1
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