Quoting Umesh Nerlige Ramappa (2019-10-21 23:52:49) > From: Lionel Landwerlin <lionel.g.landwer...@intel.com> > > The design of the OA unit has been split into several units. We now > have a global unit (OAG) and a render specific unit (OAR). This leads > to some changes on how we program things. Some details : > > OAR: > - has its own set of counter registers, they are per-context > saved/restored > - counters are not written to the circular OA buffer > - a snapshot of the counters can be acquired with > MI_RECORD_PERF_COUNT, or a single counter can be read with > MI_STORE_REGISTER_MEM. > > OAG: > - has global counters that increment across context switches > - counters are written into the circular OA buffer (if requested) > > v2: Fix checkpatch warnings on code style (Lucas) > v3: (Umesh) > - Update register from which tail, status and head are read > - Update logic to sample context reports > - Update whitelist mux and b counter regs > v4: Fix a bug when updating context image for new contexts (Umesh) > v5: Squash patch enabling save/restore of counters into context image > > We want this so we can preempt performance queries and keep the > system responsive even when long running queries are ongoing. We > avoid doing it for all contexts. > > - use LRI to modify context control (Chris) > - use MASKED_FIELD to program just the masked bits (Chris) > - disable save/restore of counters on cleanup (Chris) > > BSpec: 28727, 30021 > > Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com> > Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.rama...@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com> > --- > @@ -292,7 +293,8 @@ static u32 i915_perf_stream_paranoid = true; > #define INVALID_CTX_ID 0xffffffff > > /* On Gen8+ automatically triggered OA reports include a 'reason' field... */ > -#define OAREPORT_REASON_MASK 0x3f > +#define OAREPORT_REASON_MASK (IS_GEN(stream->perf->i915, 12) ? \ > + 0x7f : 0x3f)
Resist temptations to do implicit parameters. I can't guarantee that all the registers are correct, but the request emission etc for config setup seems fine. Acked-by: Chris Wilson <chris.p.wil...@intel.com> -Chris --------------------------------------------------------------------- Intel Corporation (UK) Limited Registered No. 1134945 (England) Registered Office: Pipers Way, Swindon SN3 1RJ VAT No: 860 2173 47 This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
