On Thu, 2019-11-28 at 18:13 +0200, Ville Syrjälä wrote:
> On Wed, Nov 27, 2019 at 04:41:25PM +0200, Stanislav Lisovskiy wrote:
> > Current consensus that it is redundant as
> > we already have skl_ddb_values struct out there,
> > also this struct contains only single member
> > which makes it unnecessary.
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 10 +++++-----
> > .../gpu/drm/i915/display/intel_display_power.c | 8 ++++----
> > drivers/gpu/drm/i915/i915_drv.h | 6 +-----
> > drivers/gpu/drm/i915/intel_pm.c | 15 +++++++--
> > ------
> > drivers/gpu/drm/i915/intel_pm.h | 4 ++--
> > 5 files changed, 19 insertions(+), 24 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 53dc310a5f6d..530832067113 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -13393,10 +13393,10 @@ static void verify_wm_state(struct
> > intel_crtc *crtc,
> > struct skl_hw_state {
> > struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
> > struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
> > - struct skl_ddb_allocation ddb;
> > + struct skl_ddb_values ddb;
> > } *hw;
> > - struct skl_ddb_allocation *sw_ddb;
> > + struct skl_ddb_values *sw_ddb;
> > struct skl_pipe_wm *sw_wm;
> > struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
> > const enum pipe pipe = crtc->pipe;
> > @@ -13415,7 +13415,7 @@ static void verify_wm_state(struct
> > intel_crtc *crtc,
> > skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
> >
> > skl_ddb_get_hw_state(dev_priv, &hw->ddb);
> > - sw_ddb = &dev_priv->wm.skl_hw.ddb;
> > + sw_ddb = &dev_priv->wm.skl_hw;
> >
> > if (INTEL_GEN(dev_priv) >= 11 &&
> > hw->ddb.enabled_slices != sw_ddb->enabled_slices)
> > @@ -14647,8 +14647,8 @@ static void
> > skl_commit_modeset_enables(struct intel_atomic_state *state)
> > unsigned int updated = 0;
> > bool progress;
> > int i;
> > - u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
> > - u8 required_slices = state->wm_results.ddb.enabled_slices;
> > + u8 hw_enabled_slices = dev_priv->wm.skl_hw.enabled_slices;
> > + u8 required_slices = state->wm_results.enabled_slices;
> > struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
> >
> > for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state, new_crtc_state, i)
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index ce1b64f4dd44..75198da13479 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -4264,7 +4264,7 @@ static u8 intel_dbuf_max_slices(struct
> > drm_i915_private *dev_priv)
> > void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
> > u8 req_slices)
> > {
> > - const u8 hw_enabled_slices = dev_priv-
> > >wm.skl_hw.ddb.enabled_slices;
> > + const u8 hw_enabled_slices = dev_priv-
> > >wm.skl_hw.enabled_slices;
> > bool ret;
> >
> > if (req_slices > intel_dbuf_max_slices(dev_priv)) {
> > @@ -4281,7 +4281,7 @@ void icl_dbuf_slices_update(struct
> > drm_i915_private *dev_priv,
> > ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2,
> > false);
> >
> > if (ret)
> > - dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices;
> > + dev_priv->wm.skl_hw.enabled_slices = req_slices;
> > }
> >
> > static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
> > @@ -4300,7 +4300,7 @@ static void icl_dbuf_enable(struct
> > drm_i915_private *dev_priv)
> > * FIXME: for now pretend that we only have 1 slice,
> > see
> > * intel_enabled_dbuf_slices_num().
> > */
> > - dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
> > + dev_priv->wm.skl_hw.enabled_slices = 1;
> > }
> >
> > static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> > @@ -4319,7 +4319,7 @@ static void icl_dbuf_disable(struct
> > drm_i915_private *dev_priv)
> > * FIXME: for now pretend that the first slice is
> > always
> > * enabled, see intel_enabled_dbuf_slices_num().
> > */
> > - dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
> > + dev_priv->wm.skl_hw.enabled_slices = 1;
> > }
> >
> > static void icl_mbus_init(struct drm_i915_private *dev_priv)
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index fdae5a919bc8..6457f8e557a2 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -798,13 +798,9 @@ static inline bool skl_ddb_entry_equal(const
> > struct skl_ddb_entry *e1,
> > return false;
> > }
> >
> > -struct skl_ddb_allocation {
> > - u8 enabled_slices; /* GEN11 has configurable 2 slices */
> > -};
> > -
> > struct skl_ddb_values {
> > unsigned dirty_pipes;
>
> Didn't I already nuke this dirty_pipes crap?
Just checked from drm-tip - it's still there :D
Anyway I don't touch it. Or do you mean I need to kill
skl_ddb_values as well?
Stan
>
> > - struct skl_ddb_allocation ddb;
> > + u8 enabled_slices; /* GEN11 has configurable 2 slices */
> > };
> >
> > struct skl_wm_level {
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 5aad9d49a528..3857ec3d2bd6 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3823,7 +3823,7 @@ static u16 intel_get_ddb_size(struct
> > drm_i915_private *dev_priv,
> > const struct intel_crtc_state
> > *crtc_state,
> > const u64 total_data_rate,
> > const int num_active,
> > - struct skl_ddb_allocation *ddb)
> > + struct skl_ddb_values *ddb)
> > {
> > const struct drm_display_mode *adjusted_mode;
> > u64 total_data_bw;
> > @@ -3859,7 +3859,7 @@ static void
> > skl_ddb_get_pipe_allocation_limits(struct drm_i915_private
> > *dev_priv,
> > const struct intel_crtc_state
> > *crtc_state,
> > const u64 total_data_rate,
> > - struct skl_ddb_allocation *ddb,
> > + struct skl_ddb_values *ddb,
> > struct skl_ddb_entry *alloc, /* out
> > */
> > int *num_active /* out */)
> > {
> > @@ -4047,7 +4047,7 @@ void skl_pipe_ddb_get_hw_state(struct
> > intel_crtc *crtc,
> > }
> >
> > void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> > - struct skl_ddb_allocation *ddb /* out */)
> > + struct skl_ddb_values *ddb /* out */)
> > {
> > ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
> > }
> > @@ -4227,7 +4227,7 @@ icl_get_total_relative_data_rate(struct
> > intel_crtc_state *crtc_state,
> >
> > static int
> > skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
> > - struct skl_ddb_allocation *ddb /* out */)
> > + struct skl_ddb_values *ddb /* out */)
> > {
> > struct drm_atomic_state *state = crtc_state->uapi.state;
> > struct drm_crtc *crtc = crtc_state->uapi.crtc;
> > @@ -5184,13 +5184,13 @@ static int
> > skl_compute_ddb(struct intel_atomic_state *state)
> > {
> > const struct drm_i915_private *dev_priv = to_i915(state-
> > >base.dev);
> > - struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
> > + struct skl_ddb_values *ddb = &state->wm_results;
> > struct intel_crtc_state *old_crtc_state;
> > struct intel_crtc_state *new_crtc_state;
> > struct intel_crtc *crtc;
> > int ret, i;
> >
> > - memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
> > + memcpy(ddb, &dev_priv->wm.skl_hw, sizeof(*ddb));
> >
> > for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state,
> > new_crtc_state, i) {
> > @@ -5666,11 +5666,10 @@ void skl_pipe_wm_get_hw_state(struct
> > intel_crtc *crtc,
> > void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
> > {
> > struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
> > - struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
> > struct intel_crtc *crtc;
> > struct intel_crtc_state *crtc_state;
> >
> > - skl_ddb_get_hw_state(dev_priv, ddb);
> > + skl_ddb_get_hw_state(dev_priv, hw);
> > for_each_intel_crtc(&dev_priv->drm, crtc) {
> > crtc_state = to_intel_crtc_state(crtc->base.state);
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.h
> > b/drivers/gpu/drm/i915/intel_pm.h
> > index b579c724b915..1d03732ff22e 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.h
> > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > @@ -17,8 +17,8 @@ struct intel_atomic_state;
> > struct intel_crtc;
> > struct intel_crtc_state;
> > struct intel_plane;
> > -struct skl_ddb_allocation;
> > struct skl_ddb_entry;
> > +struct skl_ddb_values;
> > struct skl_pipe_wm;
> > struct skl_wm_level;
> >
> > @@ -37,7 +37,7 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc
> > *crtc,
> > struct skl_ddb_entry *ddb_y,
> > struct skl_ddb_entry *ddb_uv);
> > void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> > - struct skl_ddb_allocation *ddb /* out */);
> > + struct skl_ddb_values *ddb /* out */);
> > void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > struct skl_pipe_wm *out);
> > void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> > --
> > 2.17.1
>
>
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