Due to DDB overlaps the pipe enabling sequence is not always crescent.
As the previous patch selects the smallest pipe/transcoder in the MST
stream to be master and it needs to be enabled first this changes
were needed to guarantee that.
So first lets enable all pipes that did not needed a fullmodeset so
it don't have any external dependency, this ones can overlap with
each other ddb allocations.
Then on the second loop it will enable all the pipes that needs a
modeset and don't depends on other pipes like MST master
pipe/transcoder.
Then finally all the pipes that needs a modeset and have dependency
on other pipes.
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
Cc: Matt Roper <matthew.d.ro...@intel.com>
Cc: Manasi Navare <manasi.d.nav...@intel.com>
Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 77 ++++++++++++++------
1 file changed, 56 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 1cecce2f54f8..fa58b396e084 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14566,18 +14566,24 @@ static void skl_commit_modeset_enables(struct
intel_atomic_state *state)
/*
* Whenever the number of active pipes changes, we need to make sure we
* update the pipes in the right order so that their ddb allocations
- * never overlap with eachother inbetween CRTC updates. Otherwise we'll
+ * never overlap with each other between CRTC updates. Otherwise we'll
* cause pipe underruns and other bad stuff.
+ *
+ * So first lets enable all pipes that did not needed a fullmodeset so
+ * it don't have any external dependency
*/
do {
progress = false;
- for_each_oldnew_intel_crtc_in_state(state, crtc,
old_crtc_state, new_crtc_state, i) {
- enum pipe pipe = crtc->pipe;
- bool vbl_wait = false;
- bool modeset = needs_modeset(new_crtc_state);
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ bool vbl_wait;
+
+ if (updated & BIT(crtc->pipe) ||
+ !new_crtc_state->hw.active)
+ continue;
- if (updated & BIT(crtc->pipe) ||
!new_crtc_state->hw.active)
+ if (needs_modeset(new_crtc_state))
continue;
if
(skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
@@ -14585,7 +14591,7 @@ static void skl_commit_modeset_enables(struct
intel_atomic_state *state)
INTEL_NUM_PIPES(dev_priv), i))
continue;
- updated |= BIT(pipe);
+ updated |= BIT(crtc->pipe);
entries[i] = new_crtc_state->wm.skl.ddb;
/*
@@ -14596,30 +14602,59 @@ static void skl_commit_modeset_enables(struct
intel_atomic_state *state)
*/
if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
&old_crtc_state->wm.skl.ddb) &&
- !modeset &&
state->wm_results.dirty_pipes != updated)
vbl_wait = true;
- if (modeset && is_trans_port_sync_mode(new_crtc_state))
{
- if (is_trans_port_sync_master(new_crtc_state))
- intel_update_trans_port_sync_crtcs(crtc,
-
state,
-
old_crtc_state,
-
new_crtc_state);
- else
- continue;
- } else {
- intel_update_crtc(crtc, state, old_crtc_state,
- new_crtc_state);
- }
+ intel_update_crtc(crtc, state, old_crtc_state,
+ new_crtc_state);
if (vbl_wait)
- intel_wait_for_vblank(dev_priv, pipe);
+ intel_wait_for_vblank(dev_priv, crtc->pipe);
progress = true;
}
} while (progress);
+ /*
+ * Enabling all pipes that needs a modeset and do not depends on other
+ * pipes
+ */
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ if (updated & BIT(crtc->pipe) || !new_crtc_state->hw.active)
+ continue;
+
+ if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
+ is_trans_port_sync_slave(new_crtc_state))
+ continue;
+
+ updated |= BIT(crtc->pipe);
+
+ if (is_trans_port_sync_mode(new_crtc_state))
+ intel_update_trans_port_sync_crtcs(crtc, state,
+ old_crtc_state,
+ new_crtc_state);
+ else
+ intel_update_crtc(crtc, state, old_crtc_state,
+ new_crtc_state);
+ }
+
+ /*
+ * Finally enable all pipes that needs a modeset and depends on
+ * other pipes, right now it is only MST slaves as both port sync slave
+ * and master are enabled together
+ */
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ if (updated & BIT(crtc->pipe) || !new_crtc_state->hw.active)
+ continue;
+
+ if (is_trans_port_sync_slave(new_crtc_state))
+ continue;
+
+ intel_update_crtc(crtc, state, old_crtc_state, new_crtc_state);
+ }
+
/* If 2nd DBuf slice is no more required disable it */
if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
icl_dbuf_slices_update(dev_priv, required_slices);
--
2.24.1
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