As we may try to toggle the powerwell several hundred thousand times a
second, emitting several debug messages for each event simply
overwhelms the reader, cibuglog and the filesystem!
TLDR; logging overload.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Imre Deak <imre.d...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
drivers/gpu/drm/i915/Kconfig.debug | 12 +++
.../drm/i915/display/intel_display_power.c | 74 ++++++++++---------
2 files changed, 50 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
b/drivers/gpu/drm/i915/Kconfig.debug
index 206882e154bc..8168c76aa24c 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -221,3 +221,15 @@ config DRM_I915_DEBUG_RUNTIME_PM
driver loading, suspend and resume operations.
If in doubt, say "N"
+
+config DRM_I915_DEBUG_DISPLAY_POWERWELL
+ bool "Enable extra state checking for display powerwels"
+ depends on DRM_I915
+ default n
+ help
+ Choose this option to turn on extra state checking for the
+ display powerwells (part of the runtime power management
+ functionality). This may introduce overhead during execution
+ and excessive log space consumption.
+
+ If in doubt, say "N"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b/drivers/gpu/drm/i915/display/intel_display_power.c
index 679457156797..99b32bfbbda3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -19,6 +19,12 @@
#include "intel_tc.h"
#include "intel_vga.h"
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_DISPLAY_POWERWELL)
+#define DBG(...) DRM_DEBUG_KMS(__VA_ARGS)
+#else
+#define DBG(...) do { } while (0)
+#endif
+
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
@@ -159,7 +165,7 @@ intel_display_power_domain_str(enum
intel_display_power_domain domain)
static void intel_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- DRM_DEBUG_KMS("enabling %s\n", power_well->desc->name);
+ DBG("enabling %s\n", power_well->desc->name);
power_well->desc->ops->enable(dev_priv, power_well);
power_well->hw_enabled = true;
}
@@ -167,7 +173,7 @@ static void intel_power_well_enable(struct drm_i915_private
*dev_priv,
static void intel_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- DRM_DEBUG_KMS("disabling %s\n", power_well->desc->name);
+ DBG("disabling %s\n", power_well->desc->name);
power_well->hw_enabled = false;
power_well->desc->ops->disable(dev_priv, power_well);
}
@@ -289,8 +295,7 @@ static void hsw_wait_for_power_well_enable(struct
drm_i915_private *dev_priv,
/* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
if (intel_de_wait_for_set(dev_priv, regs->driver,
HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) {
- DRM_DEBUG_KMS("%s power well enable timeout\n",
- power_well->desc->name);
+ DBG("%s power well enable timeout\n", power_well->desc->name);
/* An AUX timeout is expected if the TBT DP tunnel is down. */
WARN_ON(!power_well->desc->hsw.is_tc_tbt);
@@ -336,9 +341,9 @@ static void hsw_wait_for_power_well_disable(struct
drm_i915_private *dev_priv,
if (disabled)
return;
- DRM_DEBUG_KMS("%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",
- power_well->desc->name,
- !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
+ DBG("%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",
+ power_well->desc->name,
+ !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
}
static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
@@ -681,8 +686,7 @@ static void gen9_write_dc_state(struct drm_i915_private
*dev_priv,
/* Most of the times we need one retry, avoid spam */
if (rewrites > 1)
- DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
- state, rewrites);
+ DBG("Rewrote dc state to 0x%x %d times\n", state, rewrites);
}
static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
@@ -710,8 +714,8 @@ static void gen9_sanitize_dc_state(struct drm_i915_private
*dev_priv)
val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
- DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
- dev_priv->csr.dc_state, val);
+ DBG("Resetting DC state tracking from %02x to %02x\n",
+ dev_priv->csr.dc_state, val);
dev_priv->csr.dc_state = val;
}
@@ -748,8 +752,7 @@ static void gen9_set_dc_state(struct drm_i915_private
*dev_priv, u32 state)
val = I915_READ(DC_STATE_EN);
mask = gen9_dc_mask(dev_priv);
- DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
- val & mask, state);
+ DBG("Setting DC state from %02x to %02x\n", val & mask, state);
/* Check if DMC is ignoring our DC state requests */
if ((val & mask) != dev_priv->csr.dc_state)
@@ -791,7 +794,7 @@ sanitize_target_dc_state(struct drm_i915_private *dev_priv,
static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
{
- DRM_DEBUG_KMS("Enabling DC3CO\n");
+ DBG("Enabling DC3CO\n");
gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
}
@@ -799,7 +802,7 @@ static void tgl_disable_dc3co(struct drm_i915_private
*dev_priv)
{
u32 val;
- DRM_DEBUG_KMS("Disabling DC3CO\n");
+ DBG("Disabling DC3CO\n");
val = I915_READ(DC_STATE_EN);
val &= ~DC_STATE_DC3CO_STATUS;
I915_WRITE(DC_STATE_EN, val);
@@ -814,7 +817,7 @@ static void bxt_enable_dc9(struct drm_i915_private
*dev_priv)
{
assert_can_enable_dc9(dev_priv);
- DRM_DEBUG_KMS("Enabling DC9\n");
+ DBG("Enabling DC9\n");
/*
* Power sequencer reset is not needed on
* platforms with South Display Engine on PCH,
@@ -829,7 +832,7 @@ static void bxt_disable_dc9(struct drm_i915_private
*dev_priv)
{
assert_can_disable_dc9(dev_priv);
- DRM_DEBUG_KMS("Disabling DC9\n");
+ DBG("Disabling DC9\n");
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
@@ -928,7 +931,7 @@ static void gen9_enable_dc5(struct drm_i915_private
*dev_priv)
{
assert_can_enable_dc5(dev_priv);
- DRM_DEBUG_KMS("Enabling DC5\n");
+ DBG("Enabling DC5\n");
/* Wa Display #1183: skl,kbl,cfl */
if (IS_GEN9_BC(dev_priv))
@@ -952,7 +955,7 @@ static void skl_enable_dc6(struct drm_i915_private
*dev_priv)
{
assert_can_enable_dc6(dev_priv);
- DRM_DEBUG_KMS("Enabling DC6\n");
+ DBG("Enabling DC6\n");
/* Wa Display #1183: skl,kbl,cfl */
if (IS_GEN9_BC(dev_priv))
@@ -1529,8 +1532,8 @@ static void chv_dpio_cmn_power_well_enable(struct
drm_i915_private *dev_priv,
dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
- DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
- phy, dev_priv->chv_phy_control);
+ DBG("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
+ phy, dev_priv->chv_phy_control);
assert_chv_phy_status(dev_priv);
}
@@ -1557,8 +1560,8 @@ static void chv_dpio_cmn_power_well_disable(struct
drm_i915_private *dev_priv,
vlv_set_power_well(dev_priv, power_well, false);
- DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
- phy, dev_priv->chv_phy_control);
+ DBG("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
+ phy, dev_priv->chv_phy_control);
/* PHY is fully reset now, so we can enable the PHY state asserts */
dev_priv->chv_phy_assert[phy] = true;
@@ -1648,8 +1651,8 @@ bool chv_phy_powergate_ch(struct drm_i915_private
*dev_priv, enum dpio_phy phy,
I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
- DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d
(DPIO_PHY_CONTROL=0x%08x)\n",
- phy, ch, dev_priv->chv_phy_control);
+ DBG("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
+ phy, ch, dev_priv->chv_phy_control);
assert_chv_phy_status(dev_priv);
@@ -1679,8 +1682,8 @@ void chv_phy_powergate_lanes(struct intel_encoder
*encoder,
I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
- DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x
(PHY_CONTROL=0x%08x)\n",
- phy, ch, mask, dev_priv->chv_phy_control);
+ DBG("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
+ phy, ch, mask, dev_priv->chv_phy_control);
assert_chv_phy_status(dev_priv);
@@ -4204,8 +4207,8 @@ static u32 get_allowed_dc_mask(const struct
drm_i915_private *dev_priv,
} else if (enable_dc == -1) {
requested_dc = max_dc;
} else if (enable_dc > max_dc && enable_dc <= 4) {
- DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
- enable_dc, max_dc);
+ DBG("Adjusting requested max DC state (%d->%d)\n",
+ enable_dc, max_dc);
requested_dc = max_dc;
} else {
DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
@@ -4227,7 +4230,7 @@ static u32 get_allowed_dc_mask(const struct
drm_i915_private *dev_priv,
break;
}
- DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
+ DBG("Allowed DC state mask %02x\n", mask);
return mask;
}
@@ -4549,7 +4552,7 @@ static void hsw_write_dcomp(struct drm_i915_private
*dev_priv, u32 val)
if (IS_HASWELL(dev_priv)) {
if (sandybridge_pcode_write(dev_priv,
GEN6_PCODE_WRITE_D_COMP, val))
- DRM_DEBUG_KMS("Failed to write to D_COMP\n");
+ DBG("Failed to write to D_COMP\n");
} else {
I915_WRITE(D_COMP_BDW, val);
POSTING_READ(D_COMP_BDW);
@@ -4689,7 +4692,7 @@ static void hsw_enable_pc8(struct drm_i915_private
*dev_priv)
{
u32 val;
- DRM_DEBUG_KMS("Enabling package C8+\n");
+ DBG("Enabling package C8+\n");
if (HAS_PCH_LPT_LP(dev_priv)) {
val = I915_READ(SOUTH_DSPCLK_GATE_D);
@@ -4705,7 +4708,7 @@ static void hsw_disable_pc8(struct drm_i915_private
*dev_priv)
{
u32 val;
- DRM_DEBUG_KMS("Disabling package C8+\n");
+ DBG("Disabling package C8+\n");
hsw_restore_lcpll(dev_priv);
intel_init_pch_refclk(dev_priv);
@@ -5125,8 +5128,7 @@ static void chv_phy_control_init(struct drm_i915_private
*dev_priv)
I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
- DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
- dev_priv->chv_phy_control);
+ DBG("Initial PHY_CONTROL=0x%08x\n", dev_priv->chv_phy_control);
}
static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
@@ -5142,7 +5144,7 @@ static void vlv_cmnlane_wa(struct drm_i915_private
*dev_priv)
I915_READ(DPIO_CTL) & DPIO_CMNRST)
return;
- DRM_DEBUG_KMS("toggling display PHY side reset\n");
+ DBG("toggling display PHY side reset\n");
/* cmnlane needs DPLL registers */
disp2d->desc->ops->enable(dev_priv, disp2d);
--
2.24.1
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