On Mon, Dec 23, 2019 at 09:32:38AM -0800, Lucas De Marchi wrote:
> We are currently using a mix of platform name and acronym to name the
> functions. Let's prefer the acronym as it should be clear what platform
> it's about and it's shorter, so it doesn't go over 80 columns in a few
> cases. This converts skylake to skl where appropriate.
>
> Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
> Acked-by: Jani Nikula <jani.nik...@linux.intel.com>
> Acked-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 29 ++++++++++----------
> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
> drivers/gpu/drm/i915/display/vlv_dsi.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_mocs.c | 6 ++--
> 7 files changed, 22 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 006b1a297e6f..8435bc5a7a74 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1259,7 +1259,7 @@ static void gen11_dsi_post_disable(struct intel_encoder
> *encoder,
>
> intel_dsc_disable(old_crtc_state);
>
> - skylake_scaler_disable(old_crtc_state);
> + skl_scaler_disable(old_crtc_state);
> }
>
> static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector
> *connector,
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index d687c9503025..b52c31721755 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3896,7 +3896,7 @@ static void intel_ddi_post_disable(struct intel_encoder
> *encoder,
> intel_dsc_disable(old_crtc_state);
>
> if (INTEL_GEN(dev_priv) >= 9)
> - skylake_scaler_disable(old_crtc_state);
> + skl_scaler_disable(old_crtc_state);
> else
> ironlake_pfit_disable(old_crtc_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 14726a293171..18ac15df91c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -164,7 +164,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
> const struct intel_crtc_state *pipe_config);
> static void chv_prepare_pll(struct intel_crtc *crtc,
> const struct intel_crtc_state *pipe_config);
> -static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state);
> +static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
> static void ironlake_pfit_enable(const struct intel_crtc_state *crtc_state);
> static void intel_modeset_setup_hw_state(struct drm_device *dev,
> struct drm_modeset_acquire_ctx *ctx);
> @@ -6001,7 +6001,7 @@ static int skl_update_scaler_plane(struct
> intel_crtc_state *crtc_state,
> return 0;
> }
>
> -void skylake_scaler_disable(const struct intel_crtc_state *old_crtc_state)
> +void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> int i;
> @@ -6010,7 +6010,7 @@ void skylake_scaler_disable(const struct
> intel_crtc_state *old_crtc_state)
> skl_detach_scaler(crtc, i);
> }
>
> -static void skylake_pfit_enable(const struct intel_crtc_state *crtc_state)
> +static void skl_pfit_enable(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -6844,7 +6844,7 @@ static void hsw_crtc_enable(struct intel_atomic_state
> *state,
> glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
>
> if (INTEL_GEN(dev_priv) >= 9)
> - skylake_pfit_enable(new_crtc_state);
> + skl_pfit_enable(new_crtc_state);
> else
> ironlake_pfit_enable(new_crtc_state);
>
> @@ -10116,8 +10116,8 @@ static void ironlake_get_fdi_m_n_config(struct
> intel_crtc *crtc,
> &pipe_config->fdi_m_n, NULL);
> }
>
> -static void skylake_get_pfit_config(struct intel_crtc *crtc,
> - struct intel_crtc_state *pipe_config)
> +static void skl_get_pfit_config(struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config)
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -10148,8 +10148,8 @@ static void skylake_get_pfit_config(struct intel_crtc
> *crtc,
> }
>
> static void
> -skylake_get_initial_plane_config(struct intel_crtc *crtc,
> - struct intel_initial_plane_config
> *plane_config)
> +skl_get_initial_plane_config(struct intel_crtc *crtc,
> + struct intel_initial_plane_config *plane_config)
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -10517,9 +10517,8 @@ static void bxt_get_ddi_pll(struct drm_i915_private
> *dev_priv,
> pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
> }
>
> -static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
> - enum port port,
> - struct intel_crtc_state *pipe_config)
> +static void skl_get_ddi_pll(struct drm_i915_private *dev_priv, enum port
> port,
> + struct intel_crtc_state *pipe_config)
> {
> enum intel_dpll_id id;
> u32 temp;
> @@ -10747,7 +10746,7 @@ static void hsw_get_ddi_port_state(struct intel_crtc
> *crtc,
> else if (IS_CANNONLAKE(dev_priv))
> cannonlake_get_ddi_pll(dev_priv, port, pipe_config);
> else if (IS_GEN9_BC(dev_priv))
> - skylake_get_ddi_pll(dev_priv, port, pipe_config);
> + skl_get_ddi_pll(dev_priv, port, pipe_config);
> else if (IS_GEN9_LP(dev_priv))
> bxt_get_ddi_pll(dev_priv, port, pipe_config);
> else
> @@ -10922,7 +10921,7 @@ static bool hsw_get_pipe_config(struct intel_crtc
> *crtc,
> power_domain_mask |= BIT_ULL(power_domain);
>
> if (INTEL_GEN(dev_priv) >= 9)
> - skylake_get_pfit_config(crtc, pipe_config);
> + skl_get_pfit_config(crtc, pipe_config);
> else
> ironlake_get_pfit_config(crtc, pipe_config);
> }
> @@ -14472,7 +14471,7 @@ static void intel_pipe_fastset(const struct
> intel_crtc_state *old_crtc_state,
> skl_detach_scalers(new_crtc_state);
>
> if (new_crtc_state->pch_pfit.enabled)
> - skylake_pfit_enable(new_crtc_state);
> + skl_pfit_enable(new_crtc_state);
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> if (new_crtc_state->pch_pfit.enabled)
> ironlake_pfit_enable(new_crtc_state);
> @@ -16816,7 +16815,7 @@ void intel_init_display_hooks(struct drm_i915_private
> *dev_priv)
> if (INTEL_GEN(dev_priv) >= 9) {
> dev_priv->display.get_pipe_config = hsw_get_pipe_config;
> dev_priv->display.get_initial_plane_config =
> - skylake_get_initial_plane_config;
> + skl_get_initial_plane_config;
> dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
> dev_priv->display.crtc_enable = hsw_crtc_enable;
> dev_priv->display.crtc_disable = hsw_crtc_disable;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index 0fef9263cddc..921a584c3284 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -578,7 +578,7 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
>
> u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_center);
> int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
> -void skylake_scaler_disable(const struct intel_crtc_state *old_crtc_state);
> +void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state);
> void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state);
> u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 7aa0975c33b7..01b4608ab56c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -248,7 +248,7 @@ static void intel_mst_post_disable_dp(struct
> intel_encoder *encoder,
> intel_ddi_disable_transcoder_func(old_crtc_state);
>
> if (INTEL_GEN(dev_priv) >= 9)
> - skylake_scaler_disable(old_crtc_state);
> + skl_scaler_disable(old_crtc_state);
> else
> ironlake_pfit_disable(old_crtc_state);
>
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
> b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index 21e820299107..70ab378803c4 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -895,7 +895,7 @@ static void intel_dsi_post_disable(struct intel_encoder
> *encoder,
> if (IS_GEN9_LP(dev_priv)) {
> intel_crtc_vblank_off(old_crtc_state);
>
> - skylake_scaler_disable(old_crtc_state);
> + skl_scaler_disable(old_crtc_state);
> }
>
> if (is_vid_mode(intel_dsi)) {
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c
> b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index 893249ea48d4..cbdeda608359 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -127,7 +127,7 @@ struct drm_i915_mocs_table {
> LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), \
> L3_3_WB)
>
> -static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
> +static const struct drm_i915_mocs_entry skl_mocs_table[] = {
> GEN9_MOCS_ENTRIES,
> MOCS_ENTRY(I915_MOCS_CACHED,
> LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
> @@ -292,9 +292,9 @@ static bool get_mocs_settings(const struct
> drm_i915_private *i915,
> table->table = icelake_mocs_table;
> table->n_entries = GEN11_NUM_MOCS_ENTRIES;
> } else if (IS_GEN9_BC(i915) || IS_CANNONLAKE(i915)) {
> - table->size = ARRAY_SIZE(skylake_mocs_table);
> + table->size = ARRAY_SIZE(skl_mocs_table);
> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> - table->table = skylake_mocs_table;
> + table->table = skl_mocs_table;
> } else if (IS_GEN9_LP(i915)) {
> table->size = ARRAY_SIZE(broxton_mocs_table);
> table->n_entries = GEN9_NUM_MOCS_ENTRIES;
> --
> 2.24.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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