From: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
dgfx platforms do not support CPU fence and FBC host tracking so
lets avoid write to removed registers.
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Cc: Matt Roper <matthew.d.ro...@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
---
drivers/gpu/drm/i915/display/intel_fbc.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 1f0d24a1dec1..12900b8ce28e 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -314,7 +314,12 @@ static void gen7_fbc_activate(struct drm_i915_private
*dev_priv)
break;
}
- if (params->fence_id >= 0) {
+ if (IS_DGFX(dev_priv)) {
+ /*
+ * dGFX GPUs don't have apperture or fences and only rely on FBC
+ * render nuke to track frontbuffer modifications
+ */
+ } else if (params->fence_id >= 0) {
dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
intel_de_write(dev_priv, SNB_DPFC_CTL_SA,
SNB_CPU_FENCE_ENABLE | params->fence_id);
--
2.25.0
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