Don't immediately write the seqno into the breadcrumb slot, but wait
until we've attempted to flush the writes; that is we need to ensure the
memory is coherent prior to updating the breadcrumb so that any
observers who see the new seqno can proceed.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index b5a4b3d4ba6a..4a4792149ad6 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -446,7 +446,7 @@ static u32 *gen6_xcs_emit_breadcrumb(struct i915_request
*rq, u32 *cs)
return cs;
}
-#define GEN7_XCS_WA 32
+#define GEN7_XCS_WA 8
static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
{
int i;
@@ -454,6 +454,11 @@ static u32 *gen7_xcs_emit_breadcrumb(struct i915_request
*rq, u32 *cs)
GEM_BUG_ON(i915_request_active_timeline(rq)->hwsp_ggtt !=
rq->engine->status_page.vma);
GEM_BUG_ON(offset_in_page(i915_request_active_timeline(rq)->hwsp_offset) !=
I915_GEM_HWS_SEQNO_ADDR);
+ *cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB |
+ MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
+ *cs++ = (I915_GEM_HWS_SEQNO_ADDR + 4) | MI_FLUSH_DW_USE_GTT;
+ *cs++ = rq->fence.seqno;
+
*cs++ = MI_FLUSH_DW | MI_INVALIDATE_TLB |
MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
*cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;
@@ -461,7 +466,7 @@ static u32 *gen7_xcs_emit_breadcrumb(struct i915_request
*rq, u32 *cs)
for (i = 0; i < GEN7_XCS_WA; i++) {
*cs++ = MI_STORE_DWORD_INDEX;
- *cs++ = I915_GEM_HWS_SEQNO_ADDR;
+ *cs++ = I915_GEM_HWS_SEQNO_ADDR + 4;
*cs++ = rq->fence.seqno;
}
@@ -470,7 +475,6 @@ static u32 *gen7_xcs_emit_breadcrumb(struct i915_request
*rq, u32 *cs)
*cs++ = 0;
*cs++ = MI_USER_INTERRUPT;
- *cs++ = MI_NOOP;
rq->tail = intel_ring_offset(rq, cs);
assert_ring_tail_valid(rq->ring, rq->tail);
--
2.25.0
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