Quoting Mika Kuoppala (2020-02-07 09:44:00)
> Chris Wilson <ch...@chris-wilson.co.uk> writes:
> 
> > Quoting Patchwork (2020-02-06 18:33:34)
> >> == Series Details ==
> >> 
> >> Series: drm/i915/gt: Apply Enable Boot Fetch to MBC control register (rev2)
> >> URL   : https://patchwork.freedesktop.org/series/73107/
> >> State : failure
> >> 
> >> == Summary ==
> >> 
> >> CI Bug Log - changes from CI_DRM_7876 -> Patchwork_16465
> >> ====================================================
> >> 
> >> Summary
> >> -------
> >> 
> >>   **FAILURE**
> >> 
> >>   Serious unknown changes coming with Patchwork_16465 absolutely need to be
> >>   verified manually.
> >>   
> >>   If you think the reported changes have nothing to do with the changes
> >>   introduced in Patchwork_16465, please notify your bug team to allow them
> >>   to document this new failure mode, which will reduce false positives in 
> >> CI.
> >> 
> >>   External URL: 
> >> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16465/index.html
> >> 
> >> Possible new issues
> >> -------------------
> >> 
> >>   Here are the unknown changes that may have been introduced in 
> >> Patchwork_16465:
> >> 
> >> ### IGT changes ###
> >> 
> >> #### Possible regressions ####
> >> 
> >>   * igt@i915_selftest@live_gem:
> >>     - fi-snb-2600:        NOTRUN -> [DMESG-WARN][1] +5 similar issues
> >>    [1]: 
> >> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16465/fi-snb-2600/igt@i915_selftest@live_gem.html
> >
> > Oh well.
> 
> But this is expected as the hw will clear it at some point.

What we are reporting is that the bit does not stick after writing it.
We apply the w/a, on module load, resume and after reset; the times that
were mentioned in the excerpt as being when the HW sets it to set. It
was not mentioned that the HW would clear the bit at any other time, at
least in the doc I found (it definitely wasn't mentioned as being a
temporary bit that is cleared by HW when it completed whatever task it
performed).
-Chris
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