From: "Yokoyama, Caz" <caz.yokoy...@intel.com>
MAD_INTER_CHANNEL_0_0_0_MCHBAR:
code name offset DRAM_DDR_TYPE
SKL 0x5000 1:0 DDR4/DDR3/LPDDR3
TGL 0x6048/0x6248/0xd800 2:0 DDR4/DDR3/LPDDR3/LPDDR4
ICL 0x5000/0x6048/0x48 2:0 DDR4/DDR3/LPDDR3/LPDDR4
EHL 0x5000/0x6048 2:0 DDR4/DDR3/LPDDR3/LPDDR4
CNL 0x5000 2:0 DDR4/DDR3/LPDDR3/LPDDR4
MAD_DIMM_CH0/1_0_0_0_MCHBAR:
code name offset CH0/1
SKL 0x500c/0x5010
TGL 0x6054/0x6058
EHL 0x500c/0x5010
ICL 0x500c/0x5010
The bit definition of MAD_DIMM_CH0/1_0_0_0_MCHBAR is same between
CNL and TGL.
P_CR_MC_BIOS_REQ_0_0_0 is same on BXT and GLK in terms of its address and
bit definition.
BXT_D_CR_DRP0_DUNIT accesses offset 0x1000, 0x1200, 0x1400, 0x1600.
Its register name is RAM_ACCESS_DATA1. There is no difference between
BXT and GLK in terms of its address and bit definition.
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Matt Roper <matthew.d.ro...@intel.com>
Signed-off-by: Yokoyama, Caz <caz.yokoy...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 15 ++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 516536234e97..b9418583e503 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -806,12 +806,18 @@ skl_dram_get_channels_info(struct drm_i915_private
*dev_priv)
u32 val;
int ret;
- val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
+ if (INTEL_GEN(dev_priv) >= 12)
+ val = I915_READ(TGL_MAD_DIMM_CH0_0_0_0_MCHBAR);
+ else
+ val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
if (ret == 0)
dram_info->num_channels++;
- val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
+ if (INTEL_GEN(dev_priv) >= 12)
+ val = I915_READ(TGL_MAD_DIMM_CH1_0_0_0_MCHBAR);
+ else
+ val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
if (ret == 0)
dram_info->num_channels++;
@@ -852,7 +858,10 @@ skl_get_dram_type(struct drm_i915_private *dev_priv)
{
u32 val;
- val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
+ if (INTEL_GEN(dev_priv) >= 12)
+ val = I915_READ(TGL_MAD_INTER_CHANNEL_0_0_0_MCHBAR);
+ else
+ val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
switch (val & SKL_DRAM_DDR_TYPE_MASK) {
case SKL_DRAM_DDR_TYPE_DDR3:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b09c1d6dc0aa..9f6ec44dad6e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10508,6 +10508,9 @@ enum skl_power_gate {
#define SKL_DRAM_DDR_TYPE_LPDDR3 (2 << 0)
#define SKL_DRAM_DDR_TYPE_LPDDR4 (3 << 0)
+#define TGL_MAD_INTER_CHANNEL_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB +
0x6048)
+#define TGL_DRAM_DDR_TYPE_WIO2 (4 << 0)
+
#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB +
0x500C)
#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB +
0x5010)
#define SKL_DRAM_S_SHIFT 16
@@ -10535,6 +10538,9 @@ enum skl_power_gate {
#define CNL_DRAM_RANK_3 (0x2 << 9)
#define CNL_DRAM_RANK_4 (0x3 << 9)
+#define TGL_MAD_DIMM_CH0_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB +
0x6054)
+#define TGL_MAD_DIMM_CH1_0_0_0_MCHBAR _MMIO(MCHBAR_MIRROR_BASE_SNB +
0x6058)
+
/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this
register,
* since on HSW we can't write to it using I915_WRITE. */
#define D_COMP_HSW _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
--
2.21.0.5.gaeb582a983
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