On Sun, Feb 16, 2020 at 04:34:45PM +0000, Chris Wilson wrote:
> Read the rawclk_freq during runtime info probing, prior to its first use
> in computing the CS timestamp frequency. Then store it in the runtime
> info, and include it in the debug printouts.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/834
> Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 19 ++++++++++---------
> drivers/gpu/drm/i915/display/intel_cdclk.h | 2 +-
> .../drm/i915/display/intel_display_power.c | 9 +++------
> drivers/gpu/drm/i915/display/intel_dp.c | 10 ++++++----
> drivers/gpu/drm/i915/display/intel_panel.c | 12 +++++++-----
> drivers/gpu/drm/i915/i915_drv.h | 1 -
> drivers/gpu/drm/i915/intel_device_info.c | 7 ++++++-
> drivers/gpu/drm/i915/intel_device_info.h | 2 ++
> 8 files changed, 35 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 423c91b164b4..146c2b9bb7fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2693,28 +2693,29 @@ static int g4x_hrawclk(struct drm_i915_private
> *dev_priv)
> }
>
> /**
> - * intel_update_rawclk - Determine the current RAWCLK frequency
> + * intel_read_rawclk - Determine the current RAWCLK frequency
> * @dev_priv: i915 device
> *
> * Determine the current RAWCLK frequency. RAWCLK is a fixed
> * frequency clock so this needs to done only once.
> */
> -void intel_update_rawclk(struct drm_i915_private *dev_priv)
> +u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
> {
> + u32 freq;
> +
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
> - dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
> + freq = cnp_rawclk(dev_priv);
One thing we should perhaps also do is split the cnp+ code into
clear read and init halves. Currently this thing does both.
Anyways, patch lgtm.
Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> else if (HAS_PCH_SPLIT(dev_priv))
> - dev_priv->rawclk_freq = pch_rawclk(dev_priv);
> + freq = pch_rawclk(dev_priv);
> else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
> + freq = vlv_hrawclk(dev_priv);
> else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
> - dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
> + freq = g4x_hrawclk(dev_priv);
> else
> /* no rawclk on other platforms, or no need to know it */
> - return;
> + return 0;
>
> - drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n",
> - dev_priv->rawclk_freq);
> + return freq;
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
> b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index df21dbdcc575..5731806e4cee 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -61,7 +61,7 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
> void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
> void intel_update_cdclk(struct drm_i915_private *dev_priv);
> -void intel_update_rawclk(struct drm_i915_private *dev_priv);
> +u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
> bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
> const struct intel_cdclk_config *b);
> void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index b9a9cbad8a03..722399fc2ace 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1260,10 +1260,10 @@ static void vlv_init_display_clock_gating(struct
> drm_i915_private *dev_priv)
> MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> intel_de_write(dev_priv, CBR1_VLV, 0);
>
> - WARN_ON(dev_priv->rawclk_freq == 0);
> -
> + WARN_ON(RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
> intel_de_write(dev_priv, RAWCLK_FREQ_VLV,
> - DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
> + DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq,
> + 1000));
> }
>
> static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
> @@ -5236,9 +5236,6 @@ void intel_power_domains_init_hw(struct
> drm_i915_private *i915, bool resume)
>
> power_domains->initializing = true;
>
> - /* Must happen before power domain init on VLV/CHV */
> - intel_update_rawclk(i915);
> -
> if (INTEL_GEN(i915) >= 11) {
> icl_display_core_init(i915, resume);
> } else if (IS_CANNONLAKE(i915)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 9541ab11624d..82baf5aba84b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1213,13 +1213,14 @@ static u32 g4x_get_aux_clock_divider(struct intel_dp
> *intel_dp, int index)
> * The clock divider is based off the hrawclk, and would like to run at
> * 2MHz. So, take the hrawclk value and divide by 2000 and use that
> */
> - return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
> + return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
> }
>
> static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> + u32 freq;
>
> if (index)
> return 0;
> @@ -1230,9 +1231,10 @@ static u32 ilk_get_aux_clock_divider(struct intel_dp
> *intel_dp, int index)
> * divide by 2000 and use that
> */
> if (dig_port->aux_ch == AUX_CH_A)
> - return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
> + freq = dev_priv->cdclk.hw.cdclk;
> else
> - return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
> + freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
> + return DIV_ROUND_CLOSEST(freq, 2000);
> }
>
> static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
> @@ -6883,7 +6885,7 @@ intel_dp_init_panel_power_sequencer_registers(struct
> intel_dp *intel_dp,
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> u32 pp_on, pp_off, port_sel = 0;
> - int div = dev_priv->rawclk_freq / 1000;
> + int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
> struct pps_registers regs;
> enum port port = dp_to_dig_port(intel_dp)->base.port;
> const struct edp_power_seq *seq = &intel_dp->pps_delays;
> diff --git a/drivers/gpu/drm/i915/display/intel_panel.c
> b/drivers/gpu/drm/i915/display/intel_panel.c
> index cba2f1c2557f..585688b6ebac 100644
> --- a/drivers/gpu/drm/i915/display/intel_panel.c
> +++ b/drivers/gpu/drm/i915/display/intel_panel.c
> @@ -1406,7 +1406,8 @@ static u32 cnp_hz_to_pwm(struct intel_connector
> *connector, u32 pwm_freq_hz)
> {
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>
> - return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz);
> + return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(dev_priv)->rawclk_freq),
> + pwm_freq_hz);
> }
>
> /*
> @@ -1467,7 +1468,8 @@ static u32 pch_hz_to_pwm(struct intel_connector
> *connector, u32 pwm_freq_hz)
> {
> struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>
> - return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz * 128);
> + return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(dev_priv)->rawclk_freq),
> + pwm_freq_hz * 128);
> }
>
> /*
> @@ -1484,7 +1486,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector
> *connector, u32 pwm_freq_hz)
> int clock;
>
> if (IS_PINEVIEW(dev_priv))
> - clock = KHz(dev_priv->rawclk_freq);
> + clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq);
> else
> clock = KHz(dev_priv->cdclk.hw.cdclk);
>
> @@ -1502,7 +1504,7 @@ static u32 i965_hz_to_pwm(struct intel_connector
> *connector, u32 pwm_freq_hz)
> int clock;
>
> if (IS_G4X(dev_priv))
> - clock = KHz(dev_priv->rawclk_freq);
> + clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq);
> else
> clock = KHz(dev_priv->cdclk.hw.cdclk);
>
> @@ -1526,7 +1528,7 @@ static u32 vlv_hz_to_pwm(struct intel_connector
> *connector, u32 pwm_freq_hz)
> clock = MHz(25);
> mul = 16;
> } else {
> - clock = KHz(dev_priv->rawclk_freq);
> + clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq);
> mul = 128;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index da509d9b8895..6878e1e3f530 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -992,7 +992,6 @@ struct drm_i915_private {
> unsigned int max_cdclk_freq;
>
> unsigned int max_dotclk_freq;
> - unsigned int rawclk_freq;
> unsigned int hpll_freq;
> unsigned int fdi_pll_freq;
> unsigned int czclk_freq;
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 18d9de488593..8e99ad097830 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -24,6 +24,7 @@
>
> #include <drm/drm_print.h>
>
> +#include "display/intel_cdclk.h"
> #include "intel_device_info.h"
> #include "i915_drv.h"
>
> @@ -132,6 +133,7 @@ void intel_device_info_print_runtime(const struct
> intel_runtime_info *info,
> {
> sseu_dump(&info->sseu, p);
>
> + drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
> drm_printf(p, "CS timestamp frequency: %u kHz\n",
> info->cs_timestamp_frequency_khz);
> }
> @@ -743,7 +745,7 @@ static u32 read_timestamp_frequency(struct
> drm_i915_private *dev_priv)
> * hclks." (through the “Clocking Configuration”
> * (“CLKCFG”) MCHBAR register)
> */
> - return dev_priv->rawclk_freq / 16;
> + return RUNTIME_INFO(dev_priv)->rawclk_freq / 16;
> } else if (INTEL_GEN(dev_priv) <= 8) {
> /* PRMs say:
> *
> @@ -1043,6 +1045,9 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
> info->ppgtt_type = INTEL_PPGTT_NONE;
> }
>
> + runtime->rawclk_freq = intel_read_rawclk(dev_priv);
> + drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
> +
> /* Initialize command stream timestamp frequency */
> runtime->cs_timestamp_frequency_khz =
> read_timestamp_frequency(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index f8bfa26388c1..1ecb9df2de91 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -216,6 +216,8 @@ struct intel_runtime_info {
> /* Slice/subslice/EU info */
> struct sseu_dev_info sseu;
>
> + u32 rawclk_freq;
> +
> u32 cs_timestamp_frequency_khz;
> u32 cs_timestamp_period_ns;
>
> --
> 2.25.0
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
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