On Thu, Feb 27, 2020 at 02:00:59PM -0800, José Roberto de Souza wrote:
> It is fixed in B0 stepping.
>
> Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 22aa205793e5..a101d8072b5b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6838,8 +6838,9 @@ static void tgl_init_clock_gating(struct
> drm_i915_private *dev_priv)
> unsigned int i;
>
> /* Wa_1408615072:tgl */
> - intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,
> - 0, VSUNIT_CLKGATE_DIS_TGL);
> + if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0))
> + intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2,
> + 0, VSUNIT_CLKGATE_DIS_TGL);
I think this workaround is also implemented in the wrong location. This
is a render engine register (part of the 94D0-951C render forcewake
range on bspec 52078) and part of the MCR range (bspec 52079), so we
should program this in the engine_wa_init rather than the clock gating
function.
The ICL/EHL version (which we based the TGL WA on) is also in the wrong
place for the same reasons.
At some point we should probably audit all the other GT/engine/MCR
registers we're dealing with in the init_clock_gating functions and move
them out to more appropriate places.
Matt
>
> /* This is not a WA. Enable VD HCP & MFX_ENC powergate */
> for (i = 0; i < I915_MAX_VCS; i++) {
> --
> 2.25.1
>
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--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
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