On Thu, 2020-03-05 at 10:12 -0800, Swathi Dhanavanthri wrote:
> This workaround is to disable FF DOP Clock gating. The fix
> in B0 was backed out due to timing reasons and decided to
> be made permanent.
> Bspec: 52890
Reviewed-by: José Roberto de Souza <jose.so...@intel.com>
>
> Signed-off-by: Swathi Dhanavanthri <swathi.dhanavant...@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index cb7d85c42f13..a9d1975b5245 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1337,11 +1337,6 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
> struct drm_i915_private *i915 = engine->i915;
>
> if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> - /* Wa_1606700617:tgl */
> - wa_masked_en(wal,
> - GEN9_CS_DEBUG_MODE1,
> - FF_DOP_CLOCK_GATE_DISABLE);
> -
> /*
> * Wa_1607138336:tgl
> * Wa_1607063988:tgl
> @@ -1393,6 +1388,11 @@ rcs_engine_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_list *wal)
> /* Wa_1409804808:tgl */
> wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> GEN12_PUSH_CONST_DEREF_HOLD_DIS);
> +
> + /* Wa_1606700617:tgl */
> + wa_masked_en(wal,
> + GEN9_CS_DEBUG_MODE1,
> + FF_DOP_CLOCK_GATE_DISABLE);
> }
>
> if (IS_GEN(i915, 11)) {
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