On Thu, Mar 19, 2020 at 12:09:18PM +0530, Manna, Animesh wrote: > On 19-03-2020 01:34, Manasi Navare wrote: > > On Wed, Mar 18, 2020 at 12:05:14PM +0530, Animesh Manna wrote: > >> DP_COMP_CTL and DP_COMP_PAT register used to program DP > >> compliance pattern. > >> > >> v1: Initial patch. > >> v2: used pipe instead of port in macro definition. [Manasi] > >> v3: used trans_offset for offset calculation. [Manasi] > >> > >> Reviewed-by: Manasi Navare <manasi.d.nav...@intel.com> > >> Signed-off-by: Animesh Manna <animesh.ma...@intel.com> > >> --- > >> drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++++++++++ > >> 1 file changed, 16 insertions(+) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_reg.h > >> b/drivers/gpu/drm/i915/i915_reg.h > >> index 309cb7d96b35..8b6c9fbfe74b 100644 > >> --- a/drivers/gpu/drm/i915/i915_reg.h > >> +++ b/drivers/gpu/drm/i915/i915_reg.h > >> @@ -9792,6 +9792,22 @@ enum skl_power_gate { > >> #define DDI_BUF_BALANCE_LEG_ENABLE (1 << 31) > >> #define DDI_BUF_TRANS_HI(port, i) _MMIO(_PORT(port, > >> _DDI_BUF_TRANS_A, _DDI_BUF_TRANS_B) + (i) * 8 + 4) > >> > >> +/* DDI DP Compliance Control */ > >> +#define _DDI_DP_COMP_CTL_A 0x605F0 > >> +#define DDI_DP_COMP_CTL(pipe) _MMIO_TRANS2(pipe, > >> _DDI_DP_COMP_CTL_A) > > Any reason why you couldnt use _MMIO_PIPE2 ? > > As DP_COMP_CTL is part of transcoder register group, so I choose _MMIO_TRANS2 > for calculation. Yes _MMIO_PIPE2 will also work as the offset difference > between subsequent pipe is same (0x1000).
The preference is: 1. _MMIO_PIPE()/etc. for evenly spaced things 2. _MMIO_PIPE2()/etc. for regular but not evenly spaced stuff 3. _PICK() where the above two fail There are probably a few places that do violate that though. We should probably fix those to not give people the wrong ideas. -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx