On Tue, 31 Mar 2020 at 13:42, Chris Wilson <ch...@chris-wilson.co.uk> wrote: > > When we allocate space in the GGTT we may have to allocate a larger > region than will be populated by the object to accommodate fencing. Make > sure that this space beyond the end of the buffer points safely into > scratch space, in case the HW tries to access it anyway (e.g. fenced > access to the last tile row). > > Reported-by: Imre Deak <imre.d...@intel.com> > References: https://gitlab.freedesktop.org/drm/intel/-/issues/1554 > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: Matthew Auld <matthew.a...@intel.com> > Cc: Imre Deak <imre.d...@intel.com> > Cc: sta...@vger.kernel.org
Do we not need similar treatment for gen6? It seems to also play tricks with the nop clear range, or did we disable gen7 ppgtt in the end? Reviewed-by: Matthew Auld <matthew.a...@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
