On Mon, Apr 06, 2020 at 06:11:57PM -0700, José Roberto de Souza wrote:
> This is a expected timeout of static TC ports not conneceted, so
> not throwing warnings that would taint CI.
>
> Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 37 +++++++++++--------
> 1 file changed, 21 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 5d33929f3724..50af5854658e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -284,6 +284,21 @@ static void hsw_power_well_pre_disable(struct
> drm_i915_private *dev_priv,
> gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
> }
>
> +#define ICL_AUX_PW_TO_CH(pw_idx) \
> + ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
> +
> +#define ICL_TBT_AUX_PW_TO_CH(pw_idx) \
> + ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
> +
> +static enum aux_ch icl_tc_phy_aux_ch(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + int pw_idx = power_well->desc->hsw.idx;
> +
> + return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
> + ICL_AUX_PW_TO_CH(pw_idx);
> +}
> +
> static struct intel_digital_port *
> aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
> enum aux_ch aux_ch)
> @@ -320,11 +335,16 @@ static void hsw_wait_for_power_well_enable(struct
> drm_i915_private *dev_priv,
> /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
> if (intel_de_wait_for_set(dev_priv, regs->driver,
> HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) {
> + enum aux_ch aux_ch = icl_tc_phy_aux_ch(dev_priv, power_well);
This is only valid for ICL tc phy power wells. You could move the logic
for that to a tc_phy_aux_timeout_expected(pw_idx) helper.
> + struct intel_digital_port *dig_port =
> aux_ch_to_digital_port(dev_priv, aux_ch);
> +
> drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n",
> power_well->desc->name);
>
> /* An AUX timeout is expected if the TBT DP tunnel is down. */
> - drm_WARN_ON(&dev_priv->drm, !power_well->desc->hsw.is_tc_tbt);
> + drm_WARN_ON(&dev_priv->drm, !power_well->desc->hsw.is_tc_tbt &&
> + !(INTEL_GEN(dev_priv) == 11 &&
> dig_port->tc_legacy_port));
> +
> }
> }
>
> @@ -520,21 +540,6 @@ icl_combo_phy_aux_power_well_disable(struct
> drm_i915_private *dev_priv,
> hsw_wait_for_power_well_disable(dev_priv, power_well);
> }
>
> -#define ICL_AUX_PW_TO_CH(pw_idx) \
> - ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
> -
> -#define ICL_TBT_AUX_PW_TO_CH(pw_idx) \
> - ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
> -
> -static enum aux_ch icl_tc_phy_aux_ch(struct drm_i915_private *dev_priv,
> - struct i915_power_well *power_well)
> -{
> - int pw_idx = power_well->desc->hsw.idx;
> -
> - return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
> - ICL_AUX_PW_TO_CH(pw_idx);
> -}
> -
> #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
>
> static u64 async_put_domains_mask(struct i915_power_domains *power_domains);
> --
> 2.26.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
