On Wed, Apr 15, 2020 at 05:39:04PM +0300, Stanislav Lisovskiy wrote:
> Lets have a unified way to handle SAGV changes,
> espoecially considering the upcoming Gen12 changes.
>
> Current "standard" way of doing this in commit_tail
> is pre/post plane updates, when everything which
> has to be forbidden and not supported in new config
> has to be restricted before update and relaxed after
> plane update.
>
> v2: - Removed unneeded returns(Ville)
>
> Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>
Pushed patches 2,3,4 to dinq. Thanks.
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 13 ++++---------
> drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++++++++
> drivers/gpu/drm/i915/intel_pm.h | 2 ++
> 3 files changed, 22 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 70ec301fe6e3..ac7f600c84ca 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15349,12 +15349,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
>
> intel_set_cdclk_pre_plane_update(state);
>
> - /*
> - * SKL workaround: bspec recommends we disable the SAGV when we
> - * have more then one pipe enabled
> - */
> - if (!intel_can_enable_sagv(state))
> - intel_disable_sagv(dev_priv);
> + intel_sagv_pre_plane_update(state);
>
> intel_modeset_verify_disabled(dev_priv, state);
> }
> @@ -15451,11 +15446,11 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> intel_check_cpu_fifo_underruns(dev_priv);
> intel_check_pch_fifo_underruns(dev_priv);
>
> - if (state->modeset)
> + if (state->modeset) {
> intel_verify_planes(state);
>
> - if (state->modeset && intel_can_enable_sagv(state))
> - intel_enable_sagv(dev_priv);
> + intel_sagv_post_plane_update(state);
> + }
>
> drm_atomic_helper_commit_hw_done(&state->base);
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a0958f40e161..83a0aac31aa8 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3757,6 +3757,22 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> return 0;
> }
>
> +void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +
> + if (!intel_can_enable_sagv(state))
> + intel_disable_sagv(dev_priv);
> +}
> +
> +void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +
> + if (intel_can_enable_sagv(state))
> + intel_enable_sagv(dev_priv);
> +}
> +
> static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state
> *crtc_state)
> {
> struct drm_device *dev = crtc_state->uapi.crtc->dev;
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index d60a85421c5a..9a6036ab0f90 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -44,6 +44,8 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> bool intel_can_enable_sagv(struct intel_atomic_state *state);
> int intel_enable_sagv(struct drm_i915_private *dev_priv);
> int intel_disable_sagv(struct drm_i915_private *dev_priv);
> +void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> +void intel_sagv_post_plane_update(struct intel_atomic_state *state);
> bool skl_wm_level_equals(const struct skl_wm_level *l1,
> const struct skl_wm_level *l2);
> bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
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