On Thu, Apr 23, 2020 at 10:58:59AM +0300, Stanislav Lisovskiy wrote:
> We need a new PCode request commands and reply codes
> to be added as a prepartion patch for QGV points
> restricting for new SAGV support.
>
> v2: - Extracted those changes into separate patch
> (Ville Syrjälä)
>
> v3: - Moved new PCode masks to another place from
> PCode commands(Ville)
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> drivers/gpu/drm/i915/intel_sideband.c | 2 ++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4a1965467374..5a077a921568 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9086,6 +9086,7 @@ enum {
> #define GEN7_PCODE_ILLEGAL_DATA 0x3
> #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
> #define GEN11_PCODE_LOCKED 0x6
> +#define GEN11_PCODE_REJECTED 0x11
> #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
> #define GEN6_PCODE_WRITE_RC6VIDS 0x4
> #define GEN6_PCODE_READ_RC6VIDS 0x5
> @@ -9107,6 +9108,7 @@ enum {
> #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
> #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
> #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) <<
> 16) | (0x1 << 8))
> +#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
> #define GEN6_PCODE_READ_D_COMP 0x10
> #define GEN6_PCODE_WRITE_D_COMP 0x11
> #define ICL_PCODE_EXIT_TCCOLD 0x12
> @@ -9140,6 +9142,9 @@ enum {
> #define GEN8_GT_SLICE_INFO _MMIO(0x138064)
> #define GEN8_LSLICESTAT_MASK 0x7
>
> +#define GEN11_PCODE_POINTS_RESTRICTED 0x0
> +#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
These still look misplaced. They are things you specify to the
ICL_PCODE_SAGV_DE_MEM_SS_CONFIG command no?
In the meantime pushed patches 2,3,7. With those it looks like
we should finally have sensible sagv support for pre-icl. Yay!
> +
> #define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
> #define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
> #define CHV_SS_PG_ENABLE (1 << 1)
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c
> b/drivers/gpu/drm/i915/intel_sideband.c
> index 14daf6af6854..59ef364549cf 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -371,6 +371,8 @@ static int gen7_check_mailbox_status(u32 mbox)
> return -ENXIO;
> case GEN11_PCODE_LOCKED:
> return -EBUSY;
> + case GEN11_PCODE_REJECTED:
> + return -EACCES;
> case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> return -EOVERFLOW;
> default:
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
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