On Tue, May 05, 2020 at 01:22:45PM +0300, Stanislav Lisovskiy wrote:
> We need a new PCode request commands and reply codes
> to be added as a prepartion patch for QGV points
> restricting for new SAGV support.
>
> v2: - Extracted those changes into separate patch
> (Ville Syrjälä)
>
> v3: - Moved new PCode masks to another place from
> PCode commands(Ville)
>
> v4: - Moved new PCode masks to correspondent PCode
> command, with identation(Ville)
> - Changed naming to ICL_ instead of GEN11_
> to fit more nicely into existing definition
> style.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>
Thanks. Pushed this one.
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_sideband.c | 2 ++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fd9f2904d93c..f23a18ee28f9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9064,6 +9064,7 @@ enum {
> #define GEN7_PCODE_ILLEGAL_DATA 0x3
> #define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
> #define GEN11_PCODE_LOCKED 0x6
> +#define GEN11_PCODE_REJECTED 0x11
> #define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
> #define GEN6_PCODE_WRITE_RC6VIDS 0x4
> #define GEN6_PCODE_READ_RC6VIDS 0x5
> @@ -9085,6 +9086,9 @@ enum {
> #define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
> #define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
> #define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) <<
> 16) | (0x1 << 8))
> +#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
> +#define ICL_PCODE_POINTS_RESTRICTED 0x0
> +#define ICL_PCODE_POINTS_RESTRICTED_MASK 0x1
> #define GEN6_PCODE_READ_D_COMP 0x10
> #define GEN6_PCODE_WRITE_D_COMP 0x11
> #define ICL_PCODE_EXIT_TCCOLD 0x12
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c
> b/drivers/gpu/drm/i915/intel_sideband.c
> index d5129c1dd452..916ccd1c0e96 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -371,6 +371,8 @@ static int gen7_check_mailbox_status(u32 mbox)
> return -ENXIO;
> case GEN11_PCODE_LOCKED:
> return -EBUSY;
> + case GEN11_PCODE_REJECTED:
> + return -EACCES;
> case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> return -EOVERFLOW;
> default:
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
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