On Fri, Jul 12, 2013 at 10:03 PM, Stéphane Marchesin <marc...@chromium.org> wrote: > Otherwise the DDI_A_4_LANES bit gets lost and we can't use > 2 lanes > on eDP. This fixes eDP on hsw with > 2 lanes. > > Signed-off-by: Stéphane Marchesin <marc...@chromium.org> > --- > drivers/gpu/drm/i915/intel_ddi.c | 2 +- > drivers/gpu/drm/i915/intel_dp.c | 5 +++-- > 2 files changed, 4 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > b/drivers/gpu/drm/i915/intel_ddi.c > index 324211a..5e3f97b 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1348,7 +1348,7 @@ void intel_ddi_init(struct drm_device *dev, enum port > port) > > intel_dig_port->port = port; > intel_dig_port->port_reversal = I915_READ(DDI_BUF_CTL(port)) & > - DDI_BUF_PORT_REVERSAL; > + (DDI_BUF_PORT_REVERSAL | > DDI_A_4_LANES);
I think we should do a s/port_reversal/saved_port_bits/ since the current name is confusing. > intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); > > intel_encoder->type = INTEL_OUTPUT_UNKNOWN; > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index b739712..a1d838c 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -834,10 +834,11 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct > drm_display_mode *mode, > * configuration happens (oddly) in ironlake_pch_enable > */ > > - /* Preserve the BIOS-computed detected bit. This is > + /* Preserve the BIOS-computed detected and 4 lanes bits. This is > * supposed to be read-only. > */ > - intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; > + intel_dp->DP = I915_READ(intel_dp->output_reg) & > + (DP_DETECTED | DDI_A_4_LANES); Why is this hunk here required? It seems to not be needed for the port reversal stuff, and this code here is run on all platforms ... If possible I'd like to just ditch it. -Daniel > > /* Handle DP bits in common between all three register formats */ > intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; > -- > 1.8.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
