[Intel-gfx] [PATCH] drm/i915/gt: Trace HWSP cachelines

[Chris Wilson]

Trace the acquire/release of individual cachelines within the HWSP, so
we can look back in anger.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_timeline.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c 
b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 4546284fede1..efce02a6d69e 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -145,6 +145,10 @@ static void __cacheline_retire(struct i915_active *active)
        struct intel_timeline_cacheline *cl =
                container_of(active, typeof(*cl), active);
 
+       GT_TRACE(cl->hwsp->gt, "cacheline:%08lx retire\n",
+                i915_ggtt_offset(cl->hwsp->vma) +
+                ptr_unmask_bits(cl->vaddr, CACHELINE_BITS) * CACHELINE_BYTES);
+
        i915_vma_unpin(cl->hwsp->vma);
        if (ptr_test_bit(cl->vaddr, CACHELINE_FREE))
                __idle_cacheline_free(cl);
@@ -156,6 +160,11 @@ static int __cacheline_active(struct i915_active *active)
                container_of(active, typeof(*cl), active);
 
        __i915_vma_pin(cl->hwsp->vma);
+
+       GT_TRACE(cl->hwsp->gt, "cacheline:%08lx active\n",
+                i915_ggtt_offset(cl->hwsp->vma) +
+                ptr_unmask_bits(cl->vaddr, CACHELINE_BITS) * CACHELINE_BYTES);
+
        return 0;
 }
 
@@ -334,6 +343,9 @@ int intel_timeline_pin(struct intel_timeline *tl)
                __i915_vma_unpin(tl->hwsp_ggtt);
        }
 
+       GT_TRACE(tl->gt, "fence:%llx acquire hwsp:%08x\n",
+                tl->fence_context, tl->hwsp_offset);
+
        return 0;
 }
 
@@ -483,6 +495,9 @@ __intel_timeline_get_seqno(struct intel_timeline *tl,
        if (err)
                goto err_cacheline;
 
+       GT_TRACE(tl->gt, "fence:%llx release hwsp:%08x\n",
+                tl->fence_context, tl->hwsp_offset);
+
        cacheline_release(tl->hwsp_cacheline); /* ownership now xfered to rq */
        cacheline_free(tl->hwsp_cacheline);
 
@@ -501,6 +516,9 @@ __intel_timeline_get_seqno(struct intel_timeline *tl,
        cacheline_acquire(cl);
        tl->hwsp_cacheline = cl;
 
+       GT_TRACE(tl->gt, "fence:%llx acquire hwsp:%08x\n",
+                tl->fence_context, tl->hwsp_offset);
+
        *seqno = timeline_advance(tl);
        GEM_BUG_ON(i915_seqno_passed(*tl->hwsp_seqno, *seqno));
        return 0;
@@ -576,6 +594,9 @@ void intel_timeline_unpin(struct intel_timeline *tl)
        if (!atomic_dec_and_test(&tl->pin_count))
                return;
 
+       GT_TRACE(tl->gt, "fence:%llx release hwsp:%08x\n",
+                tl->fence_context, tl->hwsp_offset);
+
        cacheline_release(tl->hwsp_cacheline);
 
        __i915_vma_unpin(tl->hwsp_ggtt);
-- 
2.20.1

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