From: Aditya Swarup <aditya.swa...@intel.com>
Add DG1 DPLL Enable register macro and use the macro to enable the
correct DPLL based on PLL id.
Bspec: 49443, 49206
Cc: Clinton Taylor <clinton.a.tay...@intel.com>
Cc: Matt Roper <matthew.d.ro...@intel.com>
Signed-off-by: Aditya Swarup <aditya.swa...@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30 ++++++++++++-------
drivers/gpu/drm/i915/i915_reg.h | 4 +++
2 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 25c6dca096ac..0c58d8012d32 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3833,12 +3833,14 @@ static bool combo_pll_get_hw_state(struct
drm_i915_private *dev_priv,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *hw_state)
{
- i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ i915_reg_t enable_reg;
- if (IS_ELKHARTLAKE(dev_priv) &&
- pll->info->id == DPLL_ID_EHL_DPLL4) {
+ if (IS_DG1(dev_priv))
+ enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+ else if (IS_ELKHARTLAKE(dev_priv) && pll->info->id == DPLL_ID_EHL_DPLL4)
enable_reg = MG_PLL_ENABLE(0);
- }
+ else
+ enable_reg = CNL_DPLL_ENABLE(pll->info->id);
return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
}
@@ -4036,10 +4038,12 @@ static void icl_pll_enable(struct drm_i915_private
*dev_priv,
static void combo_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ i915_reg_t enable_reg;
- if (IS_ELKHARTLAKE(dev_priv) &&
- pll->info->id == DPLL_ID_EHL_DPLL4) {
+ if (IS_DG1(dev_priv)) {
+ enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+ } else if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
enable_reg = MG_PLL_ENABLE(0);
/*
@@ -4049,6 +4053,8 @@ static void combo_pll_enable(struct drm_i915_private
*dev_priv,
*/
pll->wakeref = intel_display_power_get(dev_priv,
POWER_DOMAIN_DPLL_DC_OFF);
+ } else {
+ enable_reg = CNL_DPLL_ENABLE(pll->info->id);
}
icl_pll_power_enable(dev_priv, pll, enable_reg);
@@ -4148,16 +4154,20 @@ static void icl_pll_disable(struct drm_i915_private
*dev_priv,
static void combo_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- i915_reg_t enable_reg = CNL_DPLL_ENABLE(pll->info->id);
+ i915_reg_t enable_reg;
- if (IS_ELKHARTLAKE(dev_priv) &&
- pll->info->id == DPLL_ID_EHL_DPLL4) {
+ if (IS_DG1(dev_priv)) {
+ enable_reg = DG1_DPLL_ENABLE(pll->info->id);
+ } else if (IS_ELKHARTLAKE(dev_priv) &&
+ pll->info->id == DPLL_ID_EHL_DPLL4) {
enable_reg = MG_PLL_ENABLE(0);
icl_pll_disable(dev_priv, pll, enable_reg);
intel_display_power_put(dev_priv, POWER_DOMAIN_DPLL_DC_OFF,
pll->wakeref);
return;
+ } else {
+ enable_reg = CNL_DPLL_ENABLE(pll->info->id);
}
icl_pll_disable(dev_priv, pll, enable_reg);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7d0368c69069..57f7c48034e7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10297,6 +10297,10 @@ enum skl_power_gate {
#define MG_PLL_ENABLE(tc_port) _MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
_MG_PLL2_ENABLE)
+/* DG1 PLL */
+#define DG1_DPLL_ENABLE(pll) _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+ _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
+
#define _MG_REFCLKIN_CTL_PORT1 0x16892C
#define _MG_REFCLKIN_CTL_PORT2 0x16992C
#define _MG_REFCLKIN_CTL_PORT3 0x16A92C
--
2.26.2
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