On Wed, 2020-07-08 at 16:12 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> Some platforms apply the FBC w/as in .init_clock_gating(), some
> in fbc_activate(). Move them all to .init_clock_gating() for
> consistentce. Also safer since we don't have to worry about the
> RMWs clashing with any other runtime use of the same registers.
>
Reviewed-by: José Roberto de Souza <jose.so...@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 15 ---------------
> drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++++++
> 2 files changed, 23 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 036546ce8db8..ef2eb14f6157 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -347,21 +347,6 @@ static void gen7_fbc_activate(struct drm_i915_private
> *dev_priv)
> if (dev_priv->fbc.false_color)
> dpfc_ctl |= FBC_CTL_FALSE_COLOR;
>
> - if (IS_IVYBRIDGE(dev_priv)) {
> - /* WaFbcAsynchFlipDisableFbcQueue:ivb */
> - intel_de_write(dev_priv, ILK_DISPLAY_CHICKEN1,
> - intel_de_read(dev_priv, ILK_DISPLAY_CHICKEN1) |
> ILK_FBCQ_DIS);
> - } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> - /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
> - intel_de_write(dev_priv, CHICKEN_PIPESL_1(params->crtc.pipe),
> - intel_de_read(dev_priv,
> CHICKEN_PIPESL_1(params->crtc.pipe)) | HSW_FBCQ_DIS);
> - }
> -
> - if (INTEL_GEN(dev_priv) >= 11)
> - /* Wa_1409120013:icl,ehl,tgl */
> - intel_de_write(dev_priv, ILK_DPFC_CHICKEN,
> - ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> -
> intel_de_write(dev_priv, ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
>
> intel_fbc_recompress(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2d980b83a1f1..63d1a4882727 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7098,6 +7098,10 @@ static void gen8_set_l3sqc_credits(struct
> drm_i915_private *dev_priv,
>
> static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> + /* Wa_1409120013:icl,ehl */
> + I915_WRITE(ILK_DPFC_CHICKEN,
> + ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> +
> /* This is not an Wa. Enable to reduce Sampler power */
> I915_WRITE(GEN10_DFR_RATIO_EN_AND_CHICKEN,
> I915_READ(GEN10_DFR_RATIO_EN_AND_CHICKEN) & ~DFR_DISABLE);
> @@ -7112,6 +7116,10 @@ static void tgl_init_clock_gating(struct
> drm_i915_private *dev_priv)
> u32 vd_pg_enable = 0;
> unsigned int i;
>
> + /* Wa_1409120013:tgl */
> + I915_WRITE(ILK_DPFC_CHICKEN,
> + ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
> +
> /* This is not a WA. Enable VD HCP & MFX_ENC powergate */
> for (i = 0; i < I915_MAX_VCS; i++) {
> if (HAS_ENGINE(dev_priv, _VCS(i)))
> @@ -7222,6 +7230,11 @@ static void bdw_init_clock_gating(struct
> drm_i915_private *dev_priv)
> {
> enum pipe pipe;
>
> + /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
> + I915_WRITE(CHICKEN_PIPESL_1(PIPE_A),
> + I915_READ(CHICKEN_PIPESL_1(PIPE_A)) |
> + HSW_FBCQ_DIS);
> +
> /* WaSwitchSolVfFArbitrationPriority:bdw */
> I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
>
> @@ -7269,6 +7282,11 @@ static void bdw_init_clock_gating(struct
> drm_i915_private *dev_priv)
>
> static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> + /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
> + I915_WRITE(CHICKEN_PIPESL_1(PIPE_A),
> + I915_READ(CHICKEN_PIPESL_1(PIPE_A)) |
> + HSW_FBCQ_DIS);
> +
> /* This is required by WaCatErrorRejectionIssue:hsw */
> I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> @@ -7286,6 +7304,11 @@ static void ivb_init_clock_gating(struct
> drm_i915_private *dev_priv)
>
> I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
>
> + /* WaFbcAsynchFlipDisableFbcQueue:ivb */
> + I915_WRITE(ILK_DISPLAY_CHICKEN1,
> + I915_READ(ILK_DISPLAY_CHICKEN1) |
> + ILK_FBCQ_DIS);
> +
> /* WaDisableBackToBackFlipFix:ivb */
> I915_WRITE(IVB_CHICKEN3,
> CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
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