On Fri, 2020-07-24 at 14:39 -0700, Lucas De Marchi wrote:
> From: Matt Roper <
> matthew.d.ro...@intel.com
> >
>
> DG1's vswing tables are the same for eDP and HDMI but have slight
> differences from ICL/TGL for DP.
Reviewed-by: José Roberto de Souza <jose.so...@intel.com>
>
> Bspec: 49291
> Cc: Clinton Taylor <
> clinton.a.tay...@intel.com
> >
> Cc: José Roberto de Souza <
> jose.so...@intel.com
> >
> Cc: Radhakrishna Sripada <
> radhakrishna.srip...@intel.com
> >
> Signed-off-by: Matt Roper <
> matthew.d.ro...@intel.com
> >
> Signed-off-by: Lucas De Marchi <
> lucas.demar...@intel.com
> >
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 34 ++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 714b2bc96f23..c19d5a375eba 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -582,6 +582,34 @@ static const struct cnl_ddi_buf_trans
> ehl_combo_phy_ddi_translations_dp[] = {
> { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> };
>
> +static const struct cnl_ddi_buf_trans
> dg1_combo_phy_ddi_translations_dp_hbr[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> + { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */
> + { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> + { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
> + { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> + { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
> + { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
> + { 0xC, 0x60, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
> + { 0x6, 0x7F, 0x37, 0x00, 0x08 }, /* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> +};
> +
> +static const struct cnl_ddi_buf_trans
> dg1_combo_phy_ddi_translations_dp_hbr2[] = {
> + /* NT mV Trans mV db */
> + { 0xA, 0x32, 0x3F, 0x00, 0x00 }, /* 350 350 0.0 */
> + { 0xA, 0x48, 0x35, 0x00, 0x0A }, /* 350 500 3.1 */
> + { 0xC, 0x63, 0x2F, 0x00, 0x10 }, /* 350 700 6.0 */
> + { 0x6, 0x7F, 0x2C, 0x00, 0x13 }, /* 350 900 8.2 */
> + { 0xA, 0x43, 0x3F, 0x00, 0x00 }, /* 500 500 0.0 */
> + { 0xC, 0x60, 0x36, 0x00, 0x09 }, /* 500 700 2.9 */
> + { 0x6, 0x7F, 0x30, 0x00, 0x0F }, /* 500 900 5.1 */
> + { 0xC, 0x58, 0x3F, 0x00, 0x00 }, /* 650 700 0.6 */
> + { 0x6, 0x7F, 0x35, 0x00, 0x0A }, /* 600 900 3.5 */
> + { 0x6, 0x7F, 0x3F, 0x00, 0x00 }, /* 900 900 0.0 */
> +};
> +
> struct icl_mg_phy_ddi_buf_trans {
> u32 cri_txdeemph_override_11_6;
> u32 cri_txdeemph_override_5_0;
> @@ -1034,6 +1062,12 @@ icl_get_combo_buf_trans(struct intel_encoder *encoder,
> int type, int rate,
> } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
> *n_entries =
> ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
> return icl_combo_phy_ddi_translations_edp_hbr2;
> + } else if (IS_DG1(dev_priv) && rate > 270000) {
> + *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr2);
> + return dg1_combo_phy_ddi_translations_dp_hbr2;
> + } else if (IS_DG1(dev_priv)) {
> + *n_entries = ARRAY_SIZE(dg1_combo_phy_ddi_translations_dp_hbr);
> + return dg1_combo_phy_ddi_translations_dp_hbr;
> }
>
> *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
