Gen 10+ and Gen11+ platforms specify different max plane width for
planar formats. Add max plane width for GLK and ICL based on
BSpec: 7666
Fixes: 372b9ffb5799 ("drm/i915: Fix skl+ max plane width")
Cc: Jani Nikula <jani.nik...@intel.com>
Cc: Matt Roper <matthew.d.ro...@intel.com>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Imre Deak <imre.d...@intel.com>
Signed-off-by: Aditya Swarup <aditya.swa...@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index cf1417ff54d7..59d20c351887 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4004,14 +4004,21 @@ static int skl_check_nv12_aux_surface(struct
intel_plane_state *plane_state)
const struct drm_framebuffer *fb = plane_state->hw.fb;
unsigned int rotation = plane_state->hw.rotation;
int uv_plane = 1;
- int max_width = skl_max_plane_width(fb, uv_plane, rotation);
- int max_height = 4096;
int x = plane_state->uapi.src.x1 >> 17;
int y = plane_state->uapi.src.y1 >> 17;
int w = drm_rect_width(&plane_state->uapi.src) >> 17;
int h = drm_rect_height(&plane_state->uapi.src) >> 17;
+ int max_height = 4096;
+ int max_width;
u32 offset;
+ if (INTEL_GEN(i915) >= 11)
+ max_width = icl_max_plane_width(fb, uv_plane, rotation);
+ else if (INTEL_GEN(i915) >= 10 || IS_GEMINILAKE(i915))
+ max_width = glk_max_plane_width(fb, uv_plane, rotation);
+ else
+ max_width = skl_max_plane_width(fb, uv_plane, rotation);
+
intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
offset = intel_plane_compute_aligned_offset(&x, &y,
plane_state, uv_plane);
--
2.27.0
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