To support multiple dsb instances per pipe dsb-id is passed
as argumnet in dsb-commit() and respective cmd-buffer will
be updated in actual hardware.
v1: Initial version.
v2: Improved commit description.
Signed-off-by: Animesh Manna <animesh.ma...@intel.com>
---
drivers/gpu/drm/i915/display/intel_dsb.c | 74 +++++++++++++-----------
1 file changed, 39 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
b/drivers/gpu/drm/i915/display/intel_dsb.c
index 2a9df1d7cbc5..be301cb292dc 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -210,46 +210,50 @@ void intel_dsb_commit(const struct intel_crtc_state
*crtc_state)
struct drm_i915_private *dev_priv = to_i915(dev);
enum pipe pipe = crtc->pipe;
u32 tail;
+ int i;
- if (!(dsb && dsb->free_pos))
- return;
+ for (i = 0; i < MAX_DSB_PER_PIPE; i++) {
+ dsb = crtc_state->dsb[i];
+ if (!(dsb && dsb->free_pos))
+ continue;
- if (!intel_dsb_enable_engine(dev_priv, pipe, dsb->id))
- goto reset;
+ if (!intel_dsb_enable_engine(dev_priv, pipe, dsb->id))
+ goto reset;
- if (is_dsb_busy(dev_priv, pipe, dsb->id)) {
- drm_err(&dev_priv->drm,
- "HEAD_PTR write failed - dsb engine is busy.\n");
- goto reset;
- }
- intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id),
- i915_ggtt_offset(dsb->vma));
-
- tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);
- if (tail > dsb->free_pos * 4)
- memset(&dsb->cmd_buf[dsb->free_pos], 0,
- (tail - dsb->free_pos * 4));
-
- if (is_dsb_busy(dev_priv, pipe, dsb->id)) {
- drm_err(&dev_priv->drm,
- "TAIL_PTR write failed - dsb engine is busy.\n");
- goto reset;
- }
- drm_dbg_kms(&dev_priv->drm,
- "DSB execution started - head 0x%x, tail 0x%x\n",
- i915_ggtt_offset(dsb->vma), tail);
- intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id),
- i915_ggtt_offset(dsb->vma) + tail);
- if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) {
- drm_err(&dev_priv->drm,
- "Timed out waiting for DSB workload completion.\n");
- goto reset;
- }
+ if (is_dsb_busy(dev_priv, pipe, dsb->id)) {
+ drm_err(&dev_priv->drm,
+ "HEAD_PTR write failed - dsb engine is busy\n");
+ goto reset;
+ }
+ intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id),
+ i915_ggtt_offset(dsb->vma));
+
+ tail = ALIGN(dsb->free_pos * 4, CACHELINE_BYTES);
+ if (tail > dsb->free_pos * 4)
+ memset(&dsb->cmd_buf[dsb->free_pos], 0,
+ (tail - dsb->free_pos * 4));
+
+ if (is_dsb_busy(dev_priv, pipe, dsb->id)) {
+ drm_err(&dev_priv->drm,
+ "TAIL_PTR write failed - dsb engine is busy\n");
+ goto reset;
+ }
+ drm_dbg_kms(&dev_priv->drm,
+ "DSB execution started - head 0x%x, tail 0x%x\n",
+ i915_ggtt_offset(dsb->vma), tail);
+ intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id),
+ i915_ggtt_offset(dsb->vma) + tail);
+ if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) {
+ drm_err(&dev_priv->drm,
+ "Timed out waiting for DSB workload
completion\n");
+ goto reset;
+ }
reset:
- dsb->free_pos = 0;
- dsb->ins_start_offset = 0;
- intel_dsb_disable_engine(dev_priv, pipe, dsb->id);
+ dsb->free_pos = 0;
+ dsb->ins_start_offset = 0;
+ intel_dsb_disable_engine(dev_priv, pipe, dsb->id);
+ }
}
/**
--
2.26.0
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