This patch should at least be splitted into two, all the stepping changes here
should go to a new patch.
On Fri, 2020-12-04 at 17:08 -0800, Aditya Swarup wrote:
> From: Caz Yokoyama <caz.yokoy...@intel.com>
>
> - Add the initial platform information for Alderlake-S.
> - Specify ppgtt_size value
> - Add dma_mask_size
> - Add ADLS REVIDs
> - HW tracking(Selective Update Tracking Enable) has been
> removed from ADLS. Disable PSR2 till we enable software/
> manual tracking.
>
> v2:
> - Add support for different ADLS SOC steppings to select
> correct GT/DISP stepping based on Bspec 53655 based on
> feedback from Matt Roper.(aswarup)
>
> v3:
> - Make display/gt steppings info generic for reuse with TGL and ADLS.
> - Modify the macros to reuse tgl_revids_get()
> - Add HTI support to adls device info.(mdroper)
>
> Bspec: 53597
> Bspec: 53648
> Bspec: 53655
> Bspec: 48028
> Bspec: 53650
> BSpec: 50422
>
> Cc: José Roberto de Souza <jose.so...@intel.com>
> Cc: Matt Roper <matthew.d.ro...@intel.com>
> Cc: Lucas De Marchi <lucas.demar...@intel.com>
> Cc: Anusha Srivatsa <anusha.sriva...@intel.com>
> Cc: Jani Nikula <jani.nik...@intel.com>
> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Cc: Imre Deak <imre.d...@intel.com>
> Signed-off-by: Caz Yokoyama <caz.yokoy...@intel.com>
> Signed-off-by: Aditya Swarup <aditya.swa...@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 4 +-
> drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 28 +++++++-----
> drivers/gpu/drm/i915/i915_drv.h | 45 ++++++++++++++-----
> drivers/gpu/drm/i915/i915_pci.c | 13 ++++++
> drivers/gpu/drm/i915/intel_device_info.c | 1 +
> drivers/gpu/drm/i915/intel_device_info.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> include/drm/i915_pciids.h | 13 ++++++
> 10 files changed, 86 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index fe2d90bba536..06c036e2092c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5283,7 +5283,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private
> *dev_priv)
> int config, i;
>
>
> if (IS_DG1_REVID(dev_priv, DG1_REVID_A0, DG1_REVID_A0) ||
> - IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B0))
> + IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B0))
> /* Wa_1409767108:tgl,dg1 */
> table = wa_1409767108_buddy_page_masks;
> else
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index d9a395c486d3..1771f5000a45 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -550,7 +550,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>
>
> if (dev_priv->psr.psr2_sel_fetch_enabled) {
> /* WA 1408330847 */
> - if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> + if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
> IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0))
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> DIS_RAM_BYPASS_PSR2_MAN_TRACK,
> @@ -1102,7 +1102,7 @@ static void intel_psr_disable_locked(struct intel_dp
> *intel_dp)
>
>
> /* WA 1408330847 */
> if (dev_priv->psr.psr2_sel_fetch_enabled &&
> - (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_A0) ||
> + (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_A0) ||
> IS_RKL_REVID(dev_priv, RKL_REVID_A0, RKL_REVID_A0)))
> intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> DIS_RAM_BYPASS_PSR2_MAN_TRACK, 0);
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c
> b/drivers/gpu/drm/i915/display/intel_sprite.c
> index b7e208816074..e19d4f873b94 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -3032,7 +3032,7 @@ static bool gen12_plane_supports_mc_ccs(struct
> drm_i915_private *dev_priv,
> {
> /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */
> if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) ||
> - IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
> + IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_C0))
> return false;
>
>
> return plane_id < PLANE_SPRITE4;
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 7c6b21ced56f..3db57b577a79 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -71,16 +71,24 @@ const struct i915_rev_steppings kbl_revids[] = {
> };
>
>
> const struct i915_rev_steppings tgl_uy_revids[] = {
> - [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_A0 },
> - [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_C0 },
> - [2] = { .gt_stepping = TGL_REVID_B1, .disp_stepping = TGL_REVID_C0 },
> - [3] = { .gt_stepping = TGL_REVID_C0, .disp_stepping = TGL_REVID_D0 },
> + [0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0 },
> + [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_C0 },
> + [2] = { .gt_stepping = REVID_B1, .disp_stepping = REVID_C0 },
> + [3] = { .gt_stepping = REVID_C0, .disp_stepping = REVID_D0 },
> };
>
>
> /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same
> HW */
> const struct i915_rev_steppings tgl_revids[] = {
> - [0] = { .gt_stepping = TGL_REVID_A0, .disp_stepping = TGL_REVID_B0 },
> - [1] = { .gt_stepping = TGL_REVID_B0, .disp_stepping = TGL_REVID_D0 },
> + [0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_B0 },
> + [1] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_D0 },
> +};
> +
> +const struct i915_rev_steppings adls_revids[] = {
> + [ADLS_REVID_A0] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A0
> },
> + [ADLS_REVID_A2] = { .gt_stepping = REVID_A0, .disp_stepping = REVID_A2
> },
> + [ADLS_REVID_B0] = { .gt_stepping = REVID_B0, .disp_stepping = REVID_B0
> },
> + [ADLS_REVID_G0] = { .gt_stepping = REVID_C0, .disp_stepping = REVID_B0
> },
> + [ADLS_REVID_C0] = { .gt_stepping = REVID_D0, .disp_stepping = REVID_C0
> },
> };
>
>
> static void wa_init_start(struct i915_wa_list *wal, const char *name, const
> char *engine_name)
> @@ -1250,13 +1258,13 @@ tgl_gt_workarounds_init(struct drm_i915_private
> *i915, struct i915_wa_list *wal)
> gen12_gt_workarounds_init(i915, wal);
>
>
> /* Wa_1409420604:tgl */
> - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> + if (IS_TGL_UY_GT_REVID(i915, REVID_A0, REVID_A0))
> wa_write_or(wal,
> SUBSLICE_UNIT_LEVEL_CLKGATE2,
> CPSSUNIT_CLKGATE_DIS);
>
>
> /* Wa_1607087056:tgl also know as BUG:1409180338 */
> - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
> + if (IS_TGL_UY_GT_REVID(i915, REVID_A0, REVID_A0))
> wa_write_or(wal,
> SLICE_UNIT_LEVEL_CLKGATE,
> L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> @@ -1734,7 +1742,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> struct drm_i915_private *i915 = engine->i915;
>
>
> if (IS_DG1_REVID(i915, DG1_REVID_A0, DG1_REVID_A0) ||
> - IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> + IS_TGL_UY_GT_REVID(i915, REVID_A0, REVID_A0)) {
> /*
> * Wa_1607138336:tgl[a0],dg1[a0]
> * Wa_1607063988:tgl[a0],dg1[a0]
> @@ -1744,7 +1752,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> GEN12_DISABLE_POSH_BUSY_FF_DOP_CG);
> }
>
>
> - if (IS_TGL_UY_GT_REVID(i915, TGL_REVID_A0, TGL_REVID_A0)) {
> + if (IS_TGL_UY_GT_REVID(i915, REVID_A0, REVID_A0)) {
> /*
> * Wa_1606679103:tgl
> * (see also Wa_1606682166:icl)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 37c2df19ce52..91bd262dd871 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1424,6 +1424,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE)
> #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
> #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
> +#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
> #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> #define IS_BDW_ULT(dev_priv) \
> @@ -1566,37 +1567,43 @@ extern const struct i915_rev_steppings kbl_revids[];
> (IS_JSL_EHL(p) && IS_REVID(p, since, until))
>
>
> enum {
> - TGL_REVID_A0,
> - TGL_REVID_B0,
> - TGL_REVID_B1,
> - TGL_REVID_C0,
> - TGL_REVID_D0,
> + REVID_A0,
> + REVID_A2,
> + REVID_B0,
> + REVID_B1,
> + REVID_C0,
> + REVID_D0,
> };
>
>
> #define TGL_UY_REVIDS_SIZE 4
> #define TGL_REVIDS_SIZE 2
> +#define ADLS_REVIDS_SIZE 13
>
>
> extern const struct i915_rev_steppings tgl_uy_revids[TGL_UY_REVIDS_SIZE];
> extern const struct i915_rev_steppings tgl_revids[TGL_REVIDS_SIZE];
> +extern const struct i915_rev_steppings adls_revids[ADLS_REVIDS_SIZE];
>
>
> static inline const struct i915_rev_steppings *
> tgl_revids_get(struct drm_i915_private *dev_priv)
> {
> u8 revid = INTEL_REVID(dev_priv);
> u8 size;
> - const struct i915_rev_steppings *tgl_revid_tbl;
> + const struct i915_rev_steppings *revid_tbl;
>
>
> - if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
> - tgl_revid_tbl = tgl_uy_revids;
> + if (IS_ALDERLAKE_S(dev_priv)) {
> + revid_tbl = adls_revids;
> + size = ARRAY_SIZE(adls_revids);
> + } else if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
> + revid_tbl = tgl_uy_revids;
> size = ARRAY_SIZE(tgl_uy_revids);
> } else {
> - tgl_revid_tbl = tgl_revids;
> + revid_tbl = tgl_revids;
> size = ARRAY_SIZE(tgl_revids);
> }
>
>
> revid = min_t(u8, revid, size - 1);
>
>
> - return &tgl_revid_tbl[revid];
> + return &revid_tbl[revid];
> }
>
>
> #define IS_TGL_DISP_REVID(p, since, until) \
> @@ -1628,6 +1635,24 @@ tgl_revids_get(struct drm_i915_private *dev_priv)
> #define IS_DG1_REVID(p, since, until) \
> (IS_DG1(p) && IS_REVID(p, since, until))
>
>
> +#define ADLS_REVID_A0 0x0
> +#define ADLS_REVID_A2 0x1
> +#define ADLS_REVID_B0 0x4
> +#define ADLS_REVID_G0 0x8
> +#define ADLS_REVID_C0 0xC /*Same as H0 ADLS SOC stepping*/
> +
> +extern const struct i915_rev_steppings adls_revids[];
> +
> +#define IS_ADLS_DISP_REVID(p, since, until) \
> + (IS_ALDERLAKE_S(p) && \
> + tgl_revids_get(p)->disp_stepping >= (since) && \
> + tgl_revids_get(p)->disp_stepping <= (until))
> +
> +#define IS_ADLS_GT_REVID(p, since, until) \
> + (IS_ALDERLAKE_S(p) && \
> + tgl_revids_get(p)->gt_stepping >= (since) && \
> + tgl_revids_get(p)->gt_stepping <= (until))
> +
> #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
> #define IS_GEN9_LP(dev_priv) (IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
> #define IS_GEN9_BC(dev_priv) (IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 11fe790b1969..26e4bf8bb4ef 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -925,6 +925,18 @@ static const struct intel_device_info dg1_info
> __maybe_unused = {
> .ppgtt_size = 47,
> };
>
>
> +static const struct intel_device_info adl_s_info = {
> + GEN12_FEATURES,
> + PLATFORM(INTEL_ALDERLAKE_S),
> + .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> + .require_force_probe = 1,
> + .display.has_hti = 1,
> + .display.has_psr_hw_tracking = 0,
> + .platform_engine_mask =
> + BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
> + .dma_mask_size = 46,
> +};
> +
> #undef GEN
> #undef PLATFORM
>
>
> @@ -1001,6 +1013,7 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_JSL_IDS(&jsl_info),
> INTEL_TGL_12_IDS(&tgl_info),
> INTEL_RKL_IDS(&rkl_info),
> + INTEL_ADLS_IDS(&adl_s_info),
> {0, 0, 0}
> };
> MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index ef767f04c37c..ce8c69c17b8e 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -66,6 +66,7 @@ static const char * const platform_names[] = {
> PLATFORM_NAME(TIGERLAKE),
> PLATFORM_NAME(ROCKETLAKE),
> PLATFORM_NAME(DG1),
> + PLATFORM_NAME(ALDERLAKE_S),
> };
> #undef PLATFORM_NAME
>
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
> b/drivers/gpu/drm/i915/intel_device_info.h
> index d92fa041c700..360f3f1835f5 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -84,6 +84,7 @@ enum intel_platform {
> INTEL_TIGERLAKE,
> INTEL_ROCKETLAKE,
> INTEL_DG1,
> + INTEL_ALDERLAKE_S,
> INTEL_MAX_PLATFORMS
> };
>
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index bbc73df7f753..d92616581819 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7110,7 +7110,7 @@ static void tgl_init_clock_gating(struct
> drm_i915_private *dev_priv)
> ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>
>
> /* Wa_1409825376:tgl (pre-prod)*/
> - if (IS_TGL_DISP_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_B1))
> + if (IS_TGL_DISP_REVID(dev_priv, REVID_A0, REVID_B1))
> intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_3,
> intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_3) |
> TGL_VRH_GATING_DIS);
>
>
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 931e46191047..ae53ff8462ae 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -634,4 +634,17 @@
> INTEL_VGA_DEVICE(0x4907, info), \
> INTEL_VGA_DEVICE(0x4908, info)
>
>
> +/* ADL-S */
> +#define INTEL_ADLS_IDS(info) \
> + INTEL_VGA_DEVICE(0x4680, info), \
> + INTEL_VGA_DEVICE(0x4681, info), \
> + INTEL_VGA_DEVICE(0x4682, info), \
> + INTEL_VGA_DEVICE(0x4683, info), \
> + INTEL_VGA_DEVICE(0x4690, info), \
> + INTEL_VGA_DEVICE(0x4691, info), \
> + INTEL_VGA_DEVICE(0x4692, info), \
> + INTEL_VGA_DEVICE(0x4693, info), \
> + INTEL_VGA_DEVICE(0x4698, info), \
> + INTEL_VGA_DEVICE(0x4699, info)
> +
> #endif /* _I915_PCIIDS_H */
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