[Intel-gfx] [CI 07/10] drm/i915/gt: Insert spaces into GEN3_L3LOG_SIZE/4

[Chris Wilson]

Checkpatch wants spaces, let's give it some spaces.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
Reviewed-by: Michal Wajdeczko <michal.wajdec...@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_ring_submission.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c 
b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 1a80673bc1dd..8b7cc637c432 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -730,13 +730,14 @@ static int mi_set_context(struct i915_request *rq,
 
 static int remap_l3_slice(struct i915_request *rq, int slice)
 {
+#define L3LOG_DW (GEN7_L3LOG_SIZE / sizeof(u32))
        u32 *cs, *remap_info = rq->engine->i915->l3_parity.remap_info[slice];
        int i;
 
        if (!remap_info)
                return 0;
 
-       cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2);
+       cs = intel_ring_begin(rq, L3LOG_DW * 2 + 2);
        if (IS_ERR(cs))
                return PTR_ERR(cs);
 
@@ -745,8 +746,8 @@ static int remap_l3_slice(struct i915_request *rq, int 
slice)
         * here because no other code should access these registers other than
         * at initialization time.
         */
-       *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
-       for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
+       *cs++ = MI_LOAD_REGISTER_IMM(L3LOG_DW);
+       for (i = 0; i < L3LOG_DW; i++) {
                *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
                *cs++ = remap_info[i];
        }
@@ -754,6 +755,7 @@ static int remap_l3_slice(struct i915_request *rq, int 
slice)
        intel_ring_advance(rq, cs);
 
        return 0;
+#undef L3LOG_DW
 }
 
 static int remap_l3(struct i915_request *rq)
-- 
2.20.1

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