Implement spi_read() spi_erase() spi_write() functions.
Cc: Lucas De Marchi <lucas.demar...@intel.com>
Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
Signed-off-by: Tomas Winkler <tomas.wink...@intel.com>
Signed-off-by: Alexander Usyskin <alexander.usys...@intel.com>
Signed-off-by: Vitaly Lubart <vitaly.lub...@intel.com>
---
drivers/gpu/drm/i915/spi/intel_spi_drv.c | 137 +++++++++++++++++++++++
1 file changed, 137 insertions(+)
diff --git a/drivers/gpu/drm/i915/spi/intel_spi_drv.c
b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
index a1e7171d05db..df6a461d520d 100644
--- a/drivers/gpu/drm/i915/spi/intel_spi_drv.c
+++ b/drivers/gpu/drm/i915/spi/intel_spi_drv.c
@@ -9,7 +9,10 @@
#include <linux/io.h>
#include <linux/device.h>
#include <linux/slab.h>
+#include <linux/sizes.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/platform_device.h>
+#include <linux/delay.h>
#include <spi/intel_spi.h>
struct i915_spi {
@@ -83,6 +86,33 @@ static inline u32 spi_read32(struct i915_spi *spi, u32
address)
return ioread32(base + SPI_TRIGGER_REG);
}
+static inline u64 spi_read64(struct i915_spi *spi, u32 address)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ return readq(base + SPI_TRIGGER_REG);
+}
+
+static void spi_write32(struct i915_spi *spi, u32 address, u32 data)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ iowrite32(data, base + SPI_TRIGGER_REG);
+}
+
+static void spi_write64(struct i915_spi *spi, u32 address, u64 data)
+{
+ void __iomem *base = spi->base;
+
+ iowrite32(address, base + SPI_ADDRESS_REG);
+
+ writeq(data, base + SPI_TRIGGER_REG);
+}
+
static int spi_get_access_map(struct i915_spi *spi)
{
u32 flmap1;
@@ -139,6 +169,113 @@ static int i915_spi_is_valid(struct i915_spi *spi)
return 0;
}
+__maybe_unused
+static unsigned int spi_get_region(const struct i915_spi *spi, loff_t from)
+{
+ unsigned int i;
+
+ for (i = 0; i < spi->nregions; i++) {
+ if ((spi->regions[i].offset + spi->regions[i].size - 1) > from
&&
+ spi->regions[i].offset <= from &&
+ spi->regions[i].size != 0)
+ break;
+ }
+
+ return i;
+}
+
+__maybe_unused
+static ssize_t spi_write(struct i915_spi *spi, u8 region,
+ loff_t to, size_t len, const unsigned char *buf)
+{
+ size_t i;
+ size_t len8;
+
+ spi_set_region_id(spi, region);
+
+ len8 = ALIGN_DOWN(len, sizeof(u64));
+ for (i = 0; i < len8; i += sizeof(u64)) {
+ u64 data;
+
+ memcpy(&data, &buf[i], sizeof(u64));
+ spi_write64(spi, to + i, data);
+ if (spi_error(spi))
+ return -EIO;
+ }
+
+ if (len8 != len) { /* caller ensure that write size is at least u32 */
+ u32 data;
+
+ memcpy(&data, &buf[i], sizeof(u32));
+ spi_write32(spi, to + len8, data);
+ if (spi_error(spi))
+ return -EIO;
+ }
+
+ return len;
+}
+
+__maybe_unused
+static ssize_t spi_read(struct i915_spi *spi, u8 region,
+ loff_t from, size_t len, unsigned char *buf)
+{
+ size_t i;
+ size_t len8;
+ size_t len4;
+
+ spi_set_region_id(spi, region);
+
+ len8 = ALIGN_DOWN(len, sizeof(u64));
+ for (i = 0; i < len8; i += sizeof(u64)) {
+ u64 data = spi_read64(spi, from + i);
+
+ if (spi_error(spi))
+ return -EIO;
+
+ memcpy(&buf[i], &data, sizeof(data));
+ }
+
+ len4 = len - len8;
+ if (len4 >= sizeof(u32)) {
+ u32 data = spi_read32(spi, from + i);
+
+ if (spi_error(spi))
+ return -EIO;
+ memcpy(&buf[i], &data, sizeof(data));
+ i += sizeof(u32);
+ len4 -= sizeof(u32);
+ }
+
+ if (len4 > 0) {
+ u32 data = spi_read32(spi, from + i);
+
+ if (spi_error(spi))
+ return -EIO;
+ memcpy(&buf[i], &data, len4);
+ }
+
+ return len;
+}
+
+__maybe_unused
+static ssize_t
+spi_erase(struct i915_spi *spi, u8 region, loff_t from, u64 len, u64
*fail_addr)
+{
+ u64 i;
+ const u32 block = 0x10;
+ void __iomem *base = spi->base;
+
+ for (i = 0; i < len; i += SZ_4K) {
+ iowrite32(from + i, base + SPI_ADDRESS_REG);
+ iowrite32(region << 24 | block, base + SPI_ERASE_REG);
+ /* Since the writes are via sguint
+ * we cannot do back to back erases.
+ */
+ msleep(50);
+ }
+ return len;
+}
+
static int i915_spi_init(struct i915_spi *spi, struct device *device)
{
int ret;
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
