On Fri, 2021-03-05 at 22:04 +0200, Gwan-gyeong Mun wrote: > It replaces dc3co_enabled with dc3co_exitline on intel_psr struct. > And it saves dc3co_exitline, not dc3co_enabled, so we can use > dc3co_exitline without intel_crtc_state on other psr internal function > like as intel_psr_enable_source(). > > v2: Do not mutate externally visible state in .compute_config(). (Ville) >
Reviewed-by: José Roberto de Souza <[email protected]> > Cc: Ville Syrjälä <[email protected]> > Cc: José Roberto de Souza <[email protected]> > Cc: Anshuman Gupta <[email protected]> > Signed-off-by: Gwan-gyeong Mun <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- > drivers/gpu/drm/i915/display/intel_psr.c | 10 +++++----- > 2 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 1a76e1d9de7a..45c6388fa605 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1453,7 +1453,7 @@ struct intel_psr { > bool sink_not_reliable; > bool irq_aux_error; > u16 su_x_granularity; > - bool dc3co_enabled; > + u32 dc3co_exitline; > u32 dc3co_exit_delay; > struct delayed_work dc3co_work; > struct drm_dp_vsc_sdp vsc; > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index cd434285e3b7..9c25a701943a 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -637,7 +637,7 @@ static void tgl_dc3co_disable_work(struct work_struct > *work) > > > > > static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) > { > - if (!intel_dp->psr.dc3co_enabled) > + if (!intel_dp->psr.dc3co_exitline) > return; > > > > > cancel_delayed_work(&intel_dp->psr.dc3co_work); > @@ -938,7 +938,7 @@ static void intel_psr_enable_source(struct intel_dp > *intel_dp, > > > > > psr_irq_control(intel_dp); > > > > > - if (crtc_state->dc3co_exitline) { > + if (intel_dp->psr.dc3co_exitline) { > u32 val; > > > > > /* > @@ -947,7 +947,7 @@ static void intel_psr_enable_source(struct intel_dp > *intel_dp, > */ > val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder)); > val &= ~EXITLINE_MASK; > - val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT; > + val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT; > val |= EXITLINE_ENABLE; > intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); > } > @@ -972,11 +972,11 @@ static void intel_psr_enable_locked(struct intel_dp > *intel_dp, > intel_dp->psr.psr2_enabled = crtc_state->has_psr2; > intel_dp->psr.busy_frontbuffer_bits = 0; > intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; > - intel_dp->psr.dc3co_enabled = !!crtc_state->dc3co_exitline; > intel_dp->psr.transcoder = crtc_state->cpu_transcoder; > /* DC5/DC6 requires at least 6 idle frames */ > val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6); > intel_dp->psr.dc3co_exit_delay = val; > + intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; > intel_dp->psr.psr2_sel_fetch_enabled = > crtc_state->enable_psr2_sel_fetch; > > > > > /* > @@ -1761,7 +1761,7 @@ tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned int > frontbuffer_bits, > { > mutex_lock(&intel_dp->psr.lock); > > > > > - if (!intel_dp->psr.dc3co_enabled) > + if (!intel_dp->psr.dc3co_exitline) > goto unlock; > > > > > if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active) _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
