Yeah, haven't looked too hard at the changes, hopefully the fixed numbers can work across all out BYT SKUs. I'll test more when I get my new platform next week.
Jesse Barnes, Intel Open Source Technology Center -------- Original message -------- From: Daniel Vetter <dan...@ffwll.ch> Date: 14/09/2013 4:28 AM (GMT-08:00) To: Jesse Barnes <jbar...@virtuousgeek.org> Cc: intel-gfx <intel-gfx@lists.freedesktop.org> Subject: Re: [Intel-gfx] [PATCH] Revert "drm/i915: Move Valleyview DP DPLL divisor calc to intel_dp_set_clock v2" On Sat, Sep 14, 2013 at 2:29 AM, Jesse Barnes <jbar...@virtuousgeek.org> wrote: > On Fri, 13 Sep 2013 17:27:54 -0700 > Jesse Barnes <jbar...@virtuousgeek.org> wrote: > >> This reverts commit 65ce4bf5a15fcd4d15898be47795d0550eb2325c. > > Found this was breaking eDP for me with -nightly as of today on Baley > Bay boards. > > Chris, can you verify this on your system too? I'm working on getting > a new one with eDP support to test more. Checking with my calculator the pll settings for the 1.62 clock are wrong. Can you try to just fix them? -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
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