On 2021-07-05 at 14:53:10 +0100, Matthew Auld wrote:
> The CPU domain should be static for discrete, and on DG1 we don't need
> any flushing since everything is already coherent, so really all this
> does is an object wait, for which we have an ioctl. Longer term the
> desired caching should be an immutable creation time property for the
> BO, which can be set with something like gem_create_ext.
>
> One other user is iris + userptr, which uses the set_domain to probe all
> the pages to check if the GUP succeeds, however keeping the set_domain
> around just for that seems rather scuffed. We could equally just submit
> a dummy batch, which should hopefully be good enough, otherwise adding a
> new creation time flag for userptr might be an option. Although longer
> term we will also have vm_bind, which should also be a nice fit for
> this, so adding a whole new flag is likely overkill.
>
> v2: add some more kernel doc, also add the implicit rules with caching
LGTM
Reviewed-by: Ramalingam C <ramalinga...@intel.com>
>
> Suggested-by: Daniel Vetter <dan...@ffwll.ch>
> Signed-off-by: Matthew Auld <matthew.a...@intel.com>
> Cc: Thomas Hellström <thomas.hellst...@linux.intel.com>
> Cc: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursu...@linux.intel.com>
> Cc: Jordan Justen <jordan.l.jus...@intel.com>
> Cc: Kenneth Graunke <kenn...@whitecape.org>
> Cc: Jason Ekstrand <ja...@jlekstrand.net>
> Cc: Daniel Vetter <daniel.vet...@ffwll.ch>
> Cc: Ramalingam C <ramalinga...@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_domain.c | 3 +++
> include/uapi/drm/i915_drm.h | 18 ++++++++++++++++++
> 2 files changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> index 43004bef55cb..b684a62bf3b0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
> @@ -490,6 +490,9 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void
> *data,
> u32 write_domain = args->write_domain;
> int err;
>
> + if (IS_DGFX(to_i915(dev)))
> + return -ENODEV;
> +
> /* Only handle setting domains to types used by the CPU. */
> if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS)
> return -EINVAL;
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 6f94e5e7569a..fd1a9878730c 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -900,6 +900,24 @@ struct drm_i915_gem_mmap_offset {
> *
> * All other domains are rejected.
> *
> + * Note that for discrete, starting from DG1, this is no longer supported,
> and
> + * is instead rejected. On such platforms the CPU domain is effectively
> static,
> + * where we also only support a single &drm_i915_gem_mmap_offset cache mode,
> + * which can't be set explicitly and instead depends on the object
> placements,
> + * as per the below.
> + *
> + * Implicit caching rules, starting from DG1:
> + *
> + * - If any of the object placements (see
> &drm_i915_gem_create_ext_memory_regions)
> + * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
> + * mapped as write-combined only.
> + *
> + * - Everything else is always allocated and mapped as write-back, with the
> + * guarantee that everything is also coherent with the GPU.
> + *
> + * Note that this is likely to change in the future again, where we might
> need
> + * more flexibility on future devices, so making this all explicit as part
> of a
> + * new &drm_i915_gem_create_ext extension is probable.
> */
> struct drm_i915_gem_set_domain {
> /** @handle: Handle for the object. */
> --
> 2.26.3
>
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