On Fri, Jun 25, 2021 at 04:56:00PM -0700, Jose Souza wrote:
This is now a requirement for all display 12 and newer, not only for
tigerlake.
BSpec: 50422
Cc: Gwan-gyeong Mun <gwan-gyeong....@intel.com>
Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demar...@intel.com>
Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7dc72e4a4656b..270b1f26566df 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -911,11 +911,11 @@ static bool intel_fbc_can_activate(struct intel_crtc
*crtc)
}
/*
- * Tigerlake is not supporting FBC with PSR2.
+ * Display 12+ is not supporting FBC with PSR2.
* Recommendation is to keep this combination disabled
* Bspec: 50422 HSD: 14010260002
*/
- if (fbc->state_cache.psr2_active && IS_TIGERLAKE(dev_priv)) {
+ if (fbc->state_cache.psr2_active && DISPLAY_VER(dev_priv) >= 12) {
fbc->no_fbc_reason = "not supported with PSR2";
return false;
}
--
2.32.0
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