On Tue, Jul 13, 2021 at 08:15:02PM -0700, Matt Roper wrote:
> From: Prathap Kumar Valsan <prathap.kumar.val...@intel.com>
>
> The layout of some engine contexts has changed on Xe_HP. Define the new
> offsets.
>
> Bspec: 45585, 46256
> Signed-off-by: Prathap Kumar Valsan <prathap.kumar.val...@intel.com>
> Signed-off-by: Ramalingam C <ramalinga...@intel.com>
> Signed-off-by: Venkata Ramana Nayana <venkata.ramana.nay...@intel.com>
> Signed-off-by: Akeem G Abodunrin <akeem.g.abodun...@intel.com>
> Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atw...@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 65 ++++++++++++++++++++++++++---
> 1 file changed, 59 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 7f8fe6726504..c3f5bec8ae15 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -484,6 +484,47 @@ static const u8 gen12_rcs_offsets[] = {
> END
> };
>
> +static const u8 xehp_rcs_offsets[] = {
> + NOP(1),
> + LRI(13, POSTED),
> + REG16(0x244),
> + REG(0x034),
> + REG(0x030),
> + REG(0x038),
> + REG(0x03c),
> + REG(0x168),
> + REG(0x140),
> + REG(0x110),
> + REG(0x1c0),
> + REG(0x1c4),
> + REG(0x1c8),
> + REG(0x180),
> + REG16(0x2b4),
> +
> + NOP(5),
> + LRI(9, POSTED),
> + REG16(0x3a8),
> + REG16(0x28c),
> + REG16(0x288),
> + REG16(0x284),
> + REG16(0x280),
> + REG16(0x27c),
> + REG16(0x278),
> + REG16(0x274),
> + REG16(0x270),
> +
> + LRI(3, POSTED),
> + REG(0x1b0),
> + REG16(0x5a8),
> + REG16(0x5ac),
> +
> + NOP(6),
> + LRI(1, 0),
> + REG(0x0c8),
> +
> + END
> +};
> +
> #undef END
> #undef REG16
> #undef REG
> @@ -502,7 +543,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs
> *engine)
> !intel_engine_has_relative_mmio(engine));
>
> if (engine->class == RENDER_CLASS) {
> - if (GRAPHICS_VER(engine->i915) >= 12)
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> + return xehp_rcs_offsets;
> + else if (GRAPHICS_VER(engine->i915) >= 12)
> return gen12_rcs_offsets;
> else if (GRAPHICS_VER(engine->i915) >= 11)
> return gen11_rcs_offsets;
> @@ -522,7 +565,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs
> *engine)
>
> static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
> {
> - if (GRAPHICS_VER(engine->i915) >= 12)
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> + return 0x70;
> + else if (GRAPHICS_VER(engine->i915) >= 12)
> return 0x60;
> else if (GRAPHICS_VER(engine->i915) >= 9)
> return 0x54;
> @@ -534,7 +579,9 @@ static int lrc_ring_mi_mode(const struct intel_engine_cs
> *engine)
>
> static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
> {
> - if (GRAPHICS_VER(engine->i915) >= 12)
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> + return 0x84;
> + else if (GRAPHICS_VER(engine->i915) >= 12)
> return 0x74;
> else if (GRAPHICS_VER(engine->i915) >= 9)
> return 0x68;
> @@ -578,10 +625,16 @@ static int lrc_ring_indirect_offset(const struct
> intel_engine_cs *engine)
>
> static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
> {
> - if (engine->class != RENDER_CLASS)
> - return -1;
>
> - if (GRAPHICS_VER(engine->i915) >= 12)
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> + /*
> + * Note that the CSFE context has a dummy slot for CMD_BUF_CCTL
> + * simply to match the RCS context image layout.
> + */
> + return 0xc6;
> + else if (engine->class != RENDER_CLASS)
> + return -1;
> + else if (GRAPHICS_VER(engine->i915) >= 12)
> return 0xb6;
> else if (GRAPHICS_VER(engine->i915) >= 11)
> return 0xaa;
> --
> 2.25.4
>
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