[Intel-gfx] [PATCH 16/17] drm/i915/dg2: configure TRANS_DP2_VFREQ{HIGH, LOW} for 128b/132b

[Jani Nikula]

There's a new register pair for 128b/132b mode where you need to set the
pixel clock in Hz.

Bspec: 54128
Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index d104441344c0..a003cc98312b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -550,6 +550,17 @@ static void intel_mst_enable_dp(struct intel_atomic_state 
*state,
 
        clear_act_sent(encoder, pipe_config);
 
+       if (pipe_config->port_clock > 1000000) {
+               const struct drm_display_mode *adjusted_mode =
+                       &pipe_config->hw.adjusted_mode;
+               u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
+
+               intel_de_write(dev_priv, 
TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),
+                              TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 
24));
+               intel_de_write(dev_priv, 
TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),
+                              TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 
0xffffff));
+       }
+
        intel_ddi_enable_transcoder_func(encoder, pipe_config);
 
        intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
-- 
2.20.1